Saturday, January 31st, 2015

Featured Content

Kensington Microsaver brings security to ultrabooks

 January 2015 – Kensington is a developer of the current industry standard in laptop protection which is an integrated loop connector in the edge of the chassis of most laptops. The current connector was designed for prior generation devices that incorporated optical drives and rotating storage as the driving industrial design on device thickness. The connector is the core of a mechanical... [Read more]

TJ Rogers speaks about solar at IEDM lunch

December 2014 – At the 60th IEDM (International Electron Device Meeting) they held their awards luncheon to recognize key contributors to the device processing and device development community. Along with the awards ceremony, there was a lunch time keynote presentation. This year's speaker was TJ Rogers founder of Cypress Semiconductor and Solar cell/panel manufacturer SunPower, Dr Rogers is also... [Read more]

CMOS processing advances imaging

December 2014 – At the 60th IEDM conference in San Francisco, IMEC presented a talk on using traditional CMOS processing for enhancing imaging systems. The presentation focused on the the creation of an integrated hyperspectral and multispectral imager. Typical consumer imagers have a three color spectral pickup – Red, Green, and Blue. Many industrial, medical and scientific application need... [Read more]

Connected Cars at LAAS 2014

November 2014 – The Connected Car Expo that took place before the LA Auto Show (LAAS) had a variety of speakers and topics. To of the interesting topics that came up and were discussed were (1) the sale & resale of connected cars and (2) security of the communication with the connected car. On the issue of sale and release of connected cars, the discussion focused on whether or not the technology... [Read more]

3-D Synaptic Architecture for Neuromorphic Computation

December 17 , 2014, IEDM, San Francisco—Tuo-Hung Hou from National Chiao Tung University presented a high-density 3D synaptic architecture based on self-rectifying Ta/TaOx/TiO2/Ti RRAM. The new configurations are potentially useful as energy- and cost-efficient neuromorphic computation hardware. Existing IT systems based on Si devices and von Neumann architecture suffer from the fundamental problems... [Read more]

Monolithic 3-D Integration of Variability-tolerant Convolutional Neural Network for Pattern Recognition

December 17, 2014, IEDM, San Francisco—Daniele Garbin from CEA showed the efforts to mimic biology with neural networks for pattern recognition. A new approach uses HfO2-based oxide RAM devices as binary synapses. We tested 1T-1R OxRAM devices, integrated in standard 65nm CMOS technology. The OxRAM device is composed of a 5 nm thick HfOx layer deposited by ALD embedded between a 10 nm thick Ti and... [Read more]

Monolithic 3-D Integration of Logic and Memory: Carbon Nanotube FETs, Resistive RAM, and Silicon FETs

December 17, 2014, IEDM, San Francisco—Max M. Shulaker from Stanford showed the integration of logic and memory in a 3-D IC using RRAM and carbon nano-tubes. The demonstration circuit is an FPGA routing element the combines the logic and memory functions. Monolithic 3-D integration, whereby each circuit layer is thin and is fabricated directly over the previous circuit layers on the same substrate,... [Read more]

Ultralow Power Transponder in Thin Film Circuit Technology on Foil

December 17, 2014, IEDM, San Francisco—Tung-Huei Ke from Imec demonstrated the results of an ultra low power (ULP) transponder chip (XPDR) with sub 1V operation This organic CMOS thin film circuits TFTs on foil shows promise for low power operation in IoT applications. . Ubiquitous sensing applications such as body area network (BAN) and environmental monitoring wireless sensor networks have driven... [Read more]

Digitally-Intensive RF Transceivers in Highly Scaled CMOS

December 16, 2014, IEDM, Sn Francisco—Chih-Ming Hung from MediaTek talked about the changes in architectures to implement RF transceivers to minimize the effects of device variability and process variations. The added intelligence is still constrained by the need for some device matching and device level enhancements. The strong demand for high performance affordable handsets has spurred the requirement... [Read more]

Mismatch in High-K Metal Gate Process Analog Design

December 16, 2014, IEDM, San Francisco—A. Woo from Broadcom presented their efforts in design techniques to compensate for mismatch in Hi-K metal gate processes. The optimization techniques include process, layout, and design for variability. Among the successful techniques that enhance traditional analog and RF functions in deep submicron technologies are: SoC re-architecting, digitally assisted... [Read more]