TSMC – Flow and guidelines for new CE designs
In order to address the growing need for computing and electronic processing in portable and high functionality design, TSMC, the worlds largest independent semiconductor manufacturing foundry, released their reference flow 11 for 28nm/22nm processes. The technology driver for these processes has shifted from the historic memory designs, and then processors, to the current System-On-a-Chip (SOC) devices that are targeted at the mobile and gaming communities. The form factors for the resulting Consumer Electronics (CE) device, needs advanced, processing power, memory, graphics & displays, high speed interfaces to wireless and wired networks, and sophisticated user interfaces such as touch-screens and position sensors all in one chip or package.
Since its inception, TSMC has pursued the cutting edge of the Performance / Power / Area (PPA) tradeoff curves as part of “more of Moore” philosophy for addressing the Moore’s Law principle which has driven semiconductors since the 60's. They have now brought the “more than Moore” philosophy to the forefront which is featuring not the smallest optical geometry, but is focused on functionality in analog, mixed signal, RF and power devices. These processes are on larger devices geometries including 0.13um - 1.0um bulk and epitaxial layer (EPI) CMOS that support devices up to 800V. These devices, usually operating up to 12V or 40V, are targeted for LED driver, solar, power supply (AC-DC, DC-DC, DC-AC) applications for chargers & wall cords, as well as automotive and aircraft applications. The feature offering under the two philosophies is illustrated in the following figure.
The “more than Moore” program, is now offering more than just the semiconductor wafer manufacturing, but also advanced assembly. They are now offering stacking die assembly for traditional SIP (system in package) and 3D-ICs along with advanced, high I/O count TSVs (through silicon vias) processing and assembly. To support these designs by the customers, TSMC has released new partner and in-house tools to address the complexities of the multi-chip assembly especially the thermal aspects of the design. These new capabilities are in-house to TSMC rather than through ecosystem partners as is in the past. Capabilities of the TSMC 3D-ICs program is shown in the following figure.
Most of the gaming targeted designs and mobile devices have an Analog/Mixed Signal (AMS) component to them, In order to address the needs for designers making new chips in the sub 1V operating range on a 28nm process, TSMC released a reference flow for tools and steps. The flow, shown in the figure below, is based on an example 1.6GHz Phase Locked Loop (PLL) that is representative of designs going to the process. The flow features steps addressing LDE (Layout Dependent Effects) and requires the use of high accuracy 3D Field Solvers for the correct modeling of devices and on-chip wiring for this process node.