July 27, 2010, Santa Clara, CA the IEEE Consumer Electronics Society Santa Clara Chapter hosted a panel discussion on serial port memory technology (SPMT) at Marvel Semiconductor's facility. The Steve Leibson moderated the panel comprised of the following members.
Jim Venable, President, SPMT Consortium
John Heinlein, VP Marketing, Physical IP Division, ARM
Arun Akamat, VP of Marketing, Hynix
Sehat Sutardja, CEO, Marvell
Mr. Jim Elliott, VP, Marketing & Product Planning, Samsung
Camillo Martino , CEO, Silicon Image

The panel responses were dominated by Venable and Surardja who are the prime movers for the new architectures. Sutardja stated that the latest designs with multiple processor cores and increasingly complex operations need to overcome the memory bandwidth and interface limitations to move forward. The latest smart phones have limits on available pins, power, and bandwidth especially in the graphics and video applications.

The top 4 memory vendors are making LPDDR2 parts for the smart phones, which are expected to grow to above 200 million units this year. The SPMT memories will an obvious additional offering as all of the memory vendors see this as a large and growing market.

Heinlein concurred with the assessment of a large market. He likened the market expansion as similar to that of HDMI, where many manufacturers got together to create a new set of platforms for the A-V interface market. Arm as the leader in cores and IP is always driving the technologies to higher performance. A memory controller is a direct interface to the bulk memories while the PHY is the physical interface to the data streams. Any new technology that has the potential to increase memory bandwidth without doubling the power consumption is worthy of serious consideration.

Venable added that the new memory architectures address the issues and provide an easy implementation path for replacement of parallel to serial technologies. The serial switch technology that SPMT invented allows the memory controller to switch between serial and parallel modes depending upon the data rates. The controller prevents thrashing between the two modes by sequencing the modes from parallel to serial only after the PLL locks. The command to switch forces the controller to remain in that mode until another mode switch command. The use of the serial switch technology, does not however, result in a reduced pin count for the memories. The SPMT consortium will be bringing in more memory suppliers in the future, but already there are two major vendors in the group.

The specifications are geared towards high efficiency, with clocks embedded into the data with no added overhead. The interface is specified for up to 10 cm of PCB with a BER of 10-15 or better. Signal integrity is addressed by differential lines for the data. Because the clock rides over the data, bandwidth scales automatically as parts go to smaller feature sizes. At this time, they don't think they are infringing on anyone's patents, and have filed for their own patents. Because this is a standard memory family, they will be going to JEDEC to get a standard for SPMT memories for mobile handsets.

The SPMT will not be charging royalties for the parts, but will charge members an annual maintenance fee for the use of the interface design and memories. Volume production is expected in late 2012. The memory vendors thought the timing was about right and suggested that the initial pricing might be at a premium due to the additional controller. At the same time, they noted that variables such as test times and yield will have significant affects on final pricing.

Sutardja noted that decreasing feature size gives a higher bandwidth for free. Also, smaller features permit higher levels of integration without any cost or area penalty. The packaging costs will depend on final form factor and adding complexity like stacked die will be very important. The serial memories are being developed for mobile equipment and some memory dominated consumer equipment like TV. There is no urgency to address other applications at this time, since the DDRx families are providing the needed bandwidth for the applications that are not power limited. Long term, there is going to be a transition to serial memories for all products.

The panel noted that the next big market will be in TV, where the data rates and memory size for 3D video is in conflict with the need for much lower power consumption. The consumer electronics industry is looking to reduce total power consumption by 90 percent from its peak in the latest generations of products. Most of the consumer devices use at least some sort of memory and the overall memory market is driven by the largest possible memory arrays. Unfortunately, smaller size memories are not economically realistic.

The next generation of smart phones and other handheld platforms will need to get greater memory density and bandwidth without increasing the total power consumption. One way to address the memory power issue is to convert from parallel memory arrays to serial ones.