July 27, 2010—Santa Clara, CA—The Santa Clara section of the IEEE Consumer Electronics Society hosted a presentation on a new memory structure, serial port memory technology. Jim Venable, president of the SPMT Consortium described the basic technology and the impending ecosystem.

As system requirements for mobile devices demand greater bandwidth, equipment makers are faced with a conundrum. Higher bandwidth in the same configuration requires more power, yet the handheld devices are already power limited. One proposed alternative is to replace the parallel DRAM memory interface with a set of serial links.

The goal of the SPMT is to create a set of standards for affordable, low power, high bandwidth memories that are optimized for mobile operations. The first versions of the chips will have bandwidths of 400MBytes/s with future upgrade path, to a 6.4Gbytes/s and 12.8GB/s. These bandwidths are twice as fast as LPDDR2, use half the number of pins for interconnections, and consume half the power at full bandwidth.

The driver for this architecture is the growing number and complexity of applications and functions for the mobile handsets. These new capabilities require increasing amounts of memory and memory bandwidth, and will enable the smart phones to replace many of the functions of laptop and desktop PCs.

The SPMT developed a low-risk transition from parallel memory to serial by inventing a serial switch technology that provides two functions. First, it is a plug-in replacement for existing LPDDR2. Second, at low data rates, is switches to a parallel mode to conserve power and changes to serial mode when the data rate increases. This serial switch integrates the functionality of the serial and parallel interfaces while using the power of the lowest power consumer.

To get more information and detailed technical specifications, go to their website www.spmt.org

For a more detailed coverage of the specification and technology please the article "Local IEEE consumer electronics society looks at new memories"