December 9, 2010, 3-D Architectures for Semiconductor Integration and Packaging conference, Burlingame, CA— Bob Patti, CTO at Tezzaron Semiconductor illustrated the changes in complexity when changing from wafer-level to 3-D integration. The span of interconnect densities goes from 100 to 1 million connections per square mm and may total from 1000′s to tens of millions. [...]

 December 9, 2010, 3-D Architectures for Semiconductor Integration and Packaging conference, Burlingame, CA—Hans Stork, group vice president and CTO at Applied Materials described the technology landscape for TSVs and the drivers and applications that will use these connections. The baselines for the different unit processes and their integration into a manufacturing flow for TSV last [...]

 December 9, 2010, 3-D Architectures for Semiconductor Integration and Packaging conference, Burlingame, CA—Jan Vardaman, president of TechSearch International talked about the issues in getting TSVs into high volume production. Many areas are getting past the power point levels and approaching full production status. Memories, wireless, and high-speed logic ( FPGA) are all looking into 3-D [...]

 December 8, 2010, 3-D Architectures for Semiconductor Integration and Packaging conference, Burlingame, CA—Anton Domic senior vice president at Synopsys started out noting that > 2D integration is already here in the form of stacked die and package on package technologies. There are a number of products in production using these technologies. 3-D IC integration is [...]