December 9, 2010, 3-D Architectures for Semiconductor Integration and Packaging conference, Burlingame, CA—Jan Vardaman, president of TechSearch International talked about the issues in getting TSVs into high volume production. Many areas are getting past the power point levels and approaching full production status. Memories, wireless, and high-speed logic ( FPGA) are all looking into 3-D but the cost/performance trade-off is different for each application.

Of the manufacturing areas that need attention, the via and wafer-level processes need the most work. Via fill needs better throughput from the equipment and needs to address chemistries and voidless fill to get a lower cost of ownership. Wafer processes like thinning, handling, and joining are all moving into the hard prototyping levels of R&D as the supply chain starts to look at ramping up production. Wafer singulation is another critical issue to manage as the chip stacks increase in layer count dramatically increasing the cost of single point failures.

After all of the pieces are assembled, manufacturing needs to develop new inspection and failure analysis technologies to detect pre- and post-bond interfaces and edge inspection. Better techniques are needed for via inspection for missing vias, misalignment, fill, size, and shape for the TSVs. Manufacturers need to find fast ways to determine delamination, blistering, and other defects especially between buried layers.

Manufacturing is not the only area that needs work. The industry needs realistic design guidelines and software that can handle the duplicated and inverted layers that the current generation of tools are unable to handle. The tools will require mechanical and thermal solutions in addition to the physical place and route functions of the existing design tools.

The foundries have to create reasonable design rules and qualified production lines. The IDMs can make their own tools and design rules, but the foundries are hoping to have usable design rules some time in 2012. The use of passive and then active silicon interposers and other alternatives may delay the adoption of 3-D TSV.

While all of the technical issues are being addressed, at present no one knows who will be responsible for the bump, assembly and test functions. One question is whether or not to probe the wafers before assembly, another is how to perform final testing. Since wafer thinning and singulation are not well defined, how does one specify these operations along with definitions for the substrates for the TSV chip stack and other assembly operations.

The real engineering work is just starting for mainstream adoption of TSVs in 3-D stacks. The cost and performance drivers differ for each application and many issues remain before the technology can move into the space as a good alternative for many applications.