New multi-core processor – Multi-core Expo
May 4, 2011, Multicore Expo, San Jose, CA—We talked to the Adapteva people about their high core-count, floating-point microprocessor. This chip is programmable in C using standard development tools like GCC and eclipse. An experimental test chip with this architecture had one thousand processors on the chip.
The basic microprocessor is based on a new architecture that is optimized for scaling and minimal area per core. In a 65 nm process, a single core uses a half a millimeter square. The course setup for inter-chip vacations on all four sides, and a mesh overlay carries traffic to nonadjacent cores. Inter-core communications is done through shared memory, and memory latency to another core is 1 ns per hop.
Because of its high core count, the chip is optimized for highly parallel applications like radar, image processing, and speech. Its current implementation achieves 35 gigaflops per watt, with 1 MB of dedicated address space per core, and 32 kbytes of memory on-chip. The array is designed for single thread per core and any core can achieve a throughput of eight gigabytes per second. They designed LVDS I/O to run at 1 Gb per second so they can interface easily with Altera FPGAs in their reference design. The company used standard tools and methodologies in developing this chip. They picked the Magma tool set for the implementation.
Even though the hardware seems impressive, there are number of challenges involved with using this chip. First, it uses a custom instruction set that is optimized for C programming. C++ may come out sometime in the future, but one concern is that C++ be too verbose to fit into the address space. Message passing to other cores is via pointers in the program, and each core is optimized for single thread processing. Scheduling, load-balancing, and system management are all set up manually in programming.
This arrangement makes each thread fairly deterministic, but the parallelism and efficiency are determined by the manual partitioning. The software has libraries and utilities for tasks like message passing and because programming the chip can only be done in C, there is no assembler or even a listing of assembly instructions.