July 11, 2011, IMEC technology Forum, San Francisco—Eric Beyne, scientific director advanced packaging at IMEC addressed exploiting the 3rd dimension. Planar technologies and SoCs are running into a wall.

The smart phone is the biggest driver for advanced packaging developments. Users want lower power (or equivalently longer battery life) while the designers try to cram more functions into the chips. All of these characteristics need to be optimized for high volumes and extended supply chains.

The first 3-D stacked devices just wire bonded some memory chips together with a logic chip. Even heterogeneous stacks did not use TSVs in the stack. Homogeneous stacks were optimized for low speeds and low I/O counts. Now, the high–speed stacks are using many layers and have TSVs for vertical connections.

The advent of reliable and repeatable TSVs is opening up areas for more architectural exploration by using TSVs and networks on chip for multiple levels of interconnect. These technologies allow a reduction of frequency by increasing the number of pins available and enable memory-logic sacks and analog-logic stacks that allow optimized processes for a function. As a result, the RF and antenna functions and the MEMs can be on separate substrates with the passive devices integrated in the interposers.

So far, the best way to implement TSVs seems to be via middle—after the front-end active devices are processed and before the back-end upper layers of interconnect. The processing steps are just deep etch and metal deposit, so there are no high-temperature steps to consider. The challenge is to make a 10:1 aspect ratio copper via on a thinned wafer that is temporarily attached to a carrier wafer for the processing.

The vias are very complex. The vias are 5µ in diameter and 50µ deep and can be used to connect other than adjacent layers. Not only do they have to be accurate, but the barrier layer has to maintain complete coverage and the copper fill has to be void free across thousands of contacts. Packing many dice into a small volume causes thermal issues. One interesting result is that stacking a smaller die with added "dummy" thermal µbumps on a logic chip can act as a heat spreader, reducing hot spots on the logic part.

A full thermal analysis of the proposed configuration is an important step in the design of any 3-D package. The architecture should be changed to take advantage of the locality of the additional chips and their contribution to the whole electrical and thermal performance.