Xilinx Virtex-7 2000T FPGA for full system emulation
October 25, 2011 - San Jose, CA - Xilinx introduced their new high capacity FPGA the Virtex-7 2000T. The device is single package product that is a low power replacement of multiple ASICs and ASSPs in a high performance system. The part is built with a 28nm CMOS process and uses stacked silicon technologies and Thru-Silicon-Vias (TSVs) to create a part with the capability of beign configured to 20M logic gates. The design used 6.8B transistors, and breaks the industry record for transistor count on the largest production semiconductor (non-memory), and is currently in production.
The part is built using 4 slices of FPGA cores that are connected between blocks by 10,000 TSV interconnects per slice. Each slice is connected to a 775mm-sq Silicon interposer that is built using 4 layers of interconnect on a 65nm process. By using slices and stacked die technology, the yield issues regarding a net large die size are avoided and the economics are on the order of the yield of each of the slices. The stacked die technology has found ways to address the known good die and testability isseus for creating these parts.
The device addresses current ASIC needs of Tb/s level interfaces, high capacity (~20M gagtes) low power (<30watts) and the aviliy to craete a new design in under 3 years. This product for the first time provides all of these issues in a small BGA footprint. The advantages of these features is to implement parts for system prototyping, so end designs can run at near full system speed, and allow for concurrent softwaer development along iwth the hardware. The FPGA can also be tiled into larger blocks that perform as large systems. Currently there are over 200 designs that have used this structure to build development systems for commercial and industrial designs.
Due to the large size of the design, the software development environent had to change to keep pace. The new compiler time for the product is 4X faster than before and reduced peak memory sizing 3X. The design tools are architecture aware, so they organize functions by the same slice so the slice to slice interconnect for high speed signals is minimized. This allows the high speed SERDES on the interfaces to perform optimally at the lowest power level. The part can supply unrivaled serial bandwidth with 16 x 28Gbps serial transceiver, 72 x 13Gbps serial transievers, or an aggregated 2.8Tbps which is 3X over and other monolithic solution.
The production product was demonstrated to our group and the demo board indicated it was running at 180,000 MIPS using embedded cores in the FPGA. The structure and process allow the device to operate under 30W of power and implement an equivalent system that would take four (4) large (980K gates on a monolithic FPGA) FPGAs that are interconnected at the PCB level. With the rising speeds of this device, the avg interconnect bundle on the PCB is dissipating about 8 watts each. This makes the equiv system with standard extra large FPGAs consuming upwards of 112W for the same system. This system emulation capability should help restore the 1 yr time cycle for large silicon centric solution systems.
As the Virtex=7 2000T is part of the Virtex-7 product family, the models, development tools and test benches are the transportable over the V7 family and can move known operations to their new high performance core.