Xilinx releases Zynq Development Tools
We talked with Xilinx at the ARM TechCon about some of related packages for the Zynq programmable platform. The Zynq is an ARM dual-core Cortex-A9 embedded in a programmable fabric that was released earlier this year. The family of devices has been in development for over 4 years, to optimize the architecture and create an ecosystem for development.
The product family now has development boards, emulation platforms and software, and hardware and software development and debugging tools. The nominal design methodology is a hybrid of ASIC and FPGA flows that empower parallel hardware and software development. Hardware development is on the ISE design suite or any other HDL and HLS simulation and synthesis tools , and software tools including Lauderbach Trace32, ARM DS5, and Mentor Codebench and others.
First, they are supporting open source Linux, in addition to Android, WinCE, VxWorks, ENEA OSE, FreeROS and others. Linux software developers can access a GNU tool chain including C/C++ compilers, NEON optimized runtime libraries, debuggers and a QEMU system model of the Zynq-7000. In addition, they have a wiki, and forums on their website to provide community support for development. Key drivers and APIs are included in the distribution.
For customers requiring a commercially-supported Linux distribution, PetaLogix offers its System Development Kit (SDK) Zynq Edition. It supports all phases of the embedded design flow while integrating with the implementation tools. The PetaLinux SDK includes Linux kernel, standard libraries and applications, system image builder and custom application and device driver templates. Also provided is a QEMU-based dynamic virtual Zynq platform to kick-start software development.
The benefits of the software device models and the large tool set are in enabling early and parallel hardware and software development. By using a virtual platform, the software developers can integrate a larger percentage of the code into the system before working hardware is available. This early look into the system-level functions allows for architectural optimization and better hardware-software partitioning. It also helps to identify other development requirements including embedded software, middleware, and hard and soft IP. After the soft models are verified and validated, the software is compiled and the application binaries can be run on the design. The hardware can be sent to AutoESL for high-level synthesis directly to a bitstream.
The are offering three flavors of virtual platform: QEMU open source package, Zynq software developer bundle, and Zynq system creator bundle. The QEMU is a free, standard set of models that allows early modeling and software creation. The software developer bundle is a low priced software development environment that includes simultaneous dual-core debug. The system creator adds advanced verification, TLM extensible models, advanced analysis and debug, export capabilities to the software developer, and connections to Cadence RTL flows for a much higher price.
They are partnering with Cadence to offer a full emulation system. The emulation system provides finer grained details of the design. The hard core CPU, fabric, and basic peripheral models are already integrated into the system and the designer can add TLM IP and new models to the existing models to create a full system. This system allows the design to interface with the rest of the world for validation and profiling. IP models can be in TLM, RTL, C, or any other development language. They assume that the IP includes the models, or design partners can create the new models.
The functions in the design can be run on any of the virtual platform levels. Support for the emulation and virtual platforms is planned to be through Xilinx as the first point of contact, and to Cadence if needed. All of the pieces will be available by the end of the year.