Friday, April 18th, 2014

Low Power Electronics – UCB E3S – by Kip Brown


 The 2nd Berkeley Symposium on Energy Efficient Electronic Systems was held November 3-4, 2011 to promote international collaboration in the growing research field of energy efficiency in Devices and Circuits. The Symposium was at the University of California, Berkeley, Sutardja Dai Hall, Banatao Auditorium and featured 20 research leaders from Europe, Japan, and the US who shared their perspectives on achieving ultra-low energy devices and circuits. The audience consisted of luminaries in the field, practicing technologists, server farm administrators and graduate students. The following is a summary of their presentations.

UCB E3S 2nd Symposium

Wilfried Haensch, IBM, kicked off the program with the presentation “Setting the Stage: The Need for Energy Efficient Electronics”. The advances in geometry led to the “fast and furious” high performance era, but higher speed leads to higher power. Power constraints limit the speed today leading to parallelism (multi-cores, etc.), which allows us to continue Moore’s law. The active and static power dissipation is a function of V2 (operating voltage) device and interconnect parasitics and device leakage. Advances in lithography, materials (such as SOI), help reduce operating voltage and parasitics (except leakage which has become significant.) What is needed now is design tricks, architectures, and low voltage devices to take advantage of these manufacturing improvements.

Elad Alon, of U. C. Berkeley, continued setting the stage with “Circuit and System Driven Requirements for Digital Logic Devices”. CMOS has hit a power scaling wall at about 0.5V indicating that “we can’t scale kt/q”. Cost will still be the driving force (design, process development, yield, etc.) and cost and yield of new manufacturing processes and devices must be equivalent to that of CMOS. Lowering the CMOS threshold voltage for switching (for lower voltage operation) results in higher leakage and greater effect from threshold variation. We need a device which can switch effectively at a lower threshold, maintain a high ION/IOFF ratio (target of 104 to 106) and minimize threshold variability. The next challenge area is for the device wiring and clock drivers.

Alan Seabaugh, U of Notre Dame, introduced TFETs as a possible device solution in his talk “Fulfilling Digital Logic Requirements by Tunnel Transistors”. These devices operate with a different method than those that are dominant in CMOS devices. He reported on simulation and test pattern results, done at the university, indicating that complimentary devices can be made which would be applicable to both logic and memory applications. Experimental results are encouraging but are limited by the device and process parasitics primarily contact resistance. IDON lower than expected, ION/IOFF ratio (8000) also requires improvement threshold ~120mV/dec.

Eli Yablonovitch, U. C. Berkeley, continued discussing TFETs in his talk “Tunnel Transistor Mechanism Based on Density of States Switching”, where he discussed their work and some critical parameters in TFET design. Design goals include steep switch slope (<60mV/dec.), high ION/IOFF ratio (106:1), low operating voltage and high current density (1mA/u), which he redefined as 1 milli-mho/u to be more compatible with low power design. The solution is to modulate the tunnel barrier thickness and modulate the density of states (align the conduction bands.) This is achieved using a heavily doped Esaki diode (remember back to the tunnel diode oscillator) which pushes the negative resistance switching point near zero. Various impediments including quantum mechanical repulsion, contact resistance and soft band edges need further investigation.

Dan Hutcheson, VLSI Research, Inc., delivered the Keynote – “Power: Where It Matters, When It Matters, and When It Does Not”. Social networking, the cloud and mobile computing lead the way in requiring both increased capability and low power with high performance. Power gains come free with each new technology/geometry (from tubes to transistors to bipolar ICs to CMOS). New technologies are limited by the cost to develop and design chips. 99% of transistors manufactured today are memory. Ultra low power is applicable to low speed applications such as mobile where battery life is limited. The market is driven by the replacement model, therefore, the compute and technology market will die if there is no new technology to drive the need to replace.

Naoki Yokoyama, AIST, presented the “Development of Core Technologies for Green Nanoelectronics”. He reported that since 2006 we have seen a 190X increase in traffic but only a 5.2X increase in power required, yet that is about 20% of the total power consumed today. He described the limitations of copper and suggested the use of graphine as an improved interconnect, back end packaging material and transistor. He also discussed a super lattice Phase Change Memory where only the Ge atoms move resulting in a 10 to 100X improvement in power.

Heike Riel, IBM, presented a vertical TFET structure in “Nanowire Tunnel FET's for Energy Efficiency”. This vertical “wire” structure demonstrated a “proof of principal” but like the other TFETs presented required further improvements to reach the goals.
Robert Rogenmoser, SuVolta presented “Low Transistor Variability – The Key to Energy Efficient ICs” in which he noted that SiCMOS is a moving target and that threshold variability has become critical affecting both speed and leakage. For example in the AMD Bulldozer multi-core processor, the power distribution is: memory 50% (leakage dominated), logic 40% (high speed based but can be power gated) and analog & I/O is 10% (always on). Reducing the threshold variation from 60mV to 30mV results in a 3X reduction in worst case power. This produces a very dramatic reduction in the variation in logic delay time. The area required for analog matching is similarly improved due to smaller device sizes based on the reduced variability. Thus tighter variation control in the fab would allow the designer to lower power, or add performance at the same power, and reduce supply voltage for the same operating clock speed further improving the power performance metric.

Peter Wyatt, MIT Lincoln Lab, in his presentation “Sub-Threshold Transistors and Circuits” described their sub threshold work in fully depleted SOI. There devices offer many advantages including reduced capacitances, source/drain extensions, Vth control, steeper sub-threshold slope, and more, resulting in a 20X improvement over CMOS.

Adrian Ionescu, EPFL, in his presentation; “TFET Research in the EU STEEPER Project”, reported the status of TFET research in the EU. He reiterated the limitations of CMOS and the potential for improved high speed low voltage performance with TFETs. Goals included lowering operating voltage (0.5V), hybridization of a TFET on SOICMOS (CMOS compatible), a simulation tool, models, scaling and a benchmark. At the end of year one, they have “good results but are not done.”

Tsu-Jae King Liu, U. of California, Berkeley, presented “The Path Toward Efficient Nano-Mechanical Circuits and Systems”, which discusses the idea of a Nano-MEMS level relay logic (back to the future). There is no leakage and no gate power required to hold the switch in position. Switch logic requires fewer devices for complex functions resulting in similar function areas compared to CMOS. Multiple devices (RAMs, ADCs, Adders, etc.) have been built and demonstrated up to 100MHz operation at the 65nm node. Operation at 0.5V is predicted at the 8nm node.

Gianluca Piazza, U. of Pennsylvania, presented the last paper of the day “Piezoelectric Nano-Electro-Mechanical Systems for milli-Volt and few kT Switching”. This technology is also a switch structure with a multi-layer bimorph piezo-electric beam structure. The gates can be tuned to be normally open or closed (like a P and N transistor) allowing existing logic design. Predictions indicate operating voltages of 0.5V at the 8nm node.

Contributing Editor Kip Brown can be reached at cmbjrconsulting AT

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