Nanophotonics for Communications – IEEE Nano Council
November 15, 2011, Nanotechnology Council Symposium, Santa Clara, CA--Hughes Metras from LETI described research results for nanotechnology optical communications. The photonics on silicon and 3-D integration in CMOS will help to address the power issues.
Leti is a research organization in Grenoble, France that is working on some of the main challenges facing industry and academia. They have budget, researchers, and full clean rooms and research platforms.
The drivers for this research are the increasing restrictions for power in the growing data centers. Data volumes are growing as a very high rate and the rate is increasing. This year, the world will generate 1.8 zetabytes. By 2020, total data traffic is expected to exceed yotabytes (1021 bytes). This growth has been fueled by the advent of the digital era, the post-PC time frames. The increased bandwidth and process scaling have resulted in massive growth of on-chip data traffic, from 1 to 10 Tb/second in the past 10 years.
To address some of the power issues, chip makers have changed their focus form higher clock speeds to more cores. Two cores running at 80 percent of the previous generation clock will achieve 1.5 times the performance of a single core chip at less than half the power. Forecasts are that the number of cores will reach 256 by '20 for mainstream computer chips.
A data search consumes energy. A Google search represents about 28 W/hour and a search accounts for 1.3 percent of all the electricity in the data center. At the same time, the data transmissions are being limited in the electrical space by problems with distance, signal integrity, and pin limits on the packages and boards. As data rates go up, the power to drive a byte of data across the network increases significantly.
As an alternative, optical interconnections have a bandwidth-distance product that is 106 greater than copper wires. This interconnect is low latency and economical while also eliminating crosstalk and signal integrity issues in the transport media. The bandwidth is scalable through wavelength division multiplexing and can be bidirectional on a single fiber. Solutions exist for hybrid electronic and optical data transmissions over wire and fiber.
These solutions will be necessary for the exascale computing system to achieve the data rates, power, and cost goals. The cost of the photonics can be integrated into the cost of the compute unit, since higher levels of integration usually resulting lower costs and higher performance.
The applications for this hybrid electrical-optical interconnect will be in the WAN and on-chip. Within the enterprise, rack-to-rack and board-to-board connections will be able to run at higher speeds with lower power than the copper-only implementations. Silicon has many good characteristics for this application. It is transparent in the near IR and is the base material for the CMOS circuitry, so is relatively low cost. The challenges include the inability to detect 1.2-1.6 µ detectors and the relative difficulty in coupling to fibers. Although some people have gotten emissions in these wavelengths, silicon is a very poor emitter.
Instead, they advocate a set of modular building blocks of laser, optical switches, photodetectors, waveguides, and in-plane and grating couplers. These would be integrated into the CMOS chip to provide the integrated communications capabilities. Ge photodetectors can be mounted on the Si die and the Si can be processed to form waveguides. The SiO2 can be configured to be ribbed or strip patterns to funnel the light to the modulators or detectors. Ribs have low cost while strips have smaller size. The various patterns are all passive, so they do not consume any additional power.
The optical components for communications are emitters, detectors, and modulators. External modulation is more efficient, but also more complex. A Si modulator can work in a depletion mode and the structures are evolving from a PN junction to a PIPIN structure. Some research modulators have achieved over 40 Gb/s with a 10 dB extinguish ratio.
Detectors can be made compatible with Si for broadband, high bandwidth data. Detectors need a responsiveness of over 0.8 A/W and low dark current. Ge epitaxy on Si is a good combination. The structures can be vertical with top and bottom contacts, or lateral with a higher bandwidth and lower dark current. Either of these are relatively easy to integrate on silicon and both can get bandwidths over 120Gb/s.
The emitters are hard. Si is a very poor emitter at the ranges desired, so III-V compounds are the best alternative. The difficulty is in growing a III-V compound on a Si substrate. Instead, an easier alternative is to attach a flip-chip laser to the Si which avoids the lattice mismatch issues. This process has to be done on a per die basis because it is too wasteful and inefficient to go with a wafer-to-wafer bonding process.
Directly bonding an InP or other III-V laser on to an SOI substrate allows for a low temperature bonding process. The laser cavity can be patterned into the Si, so integrating the laser on the CMOS just requires a high degree of attachment accuracy. After thinning, the waveguide is defined by the lithography post attach.
The technologies for photonics and CMOS are usually not compatible, so systems-level integration calls for a stacked die approach with TSVs. This is a standard die-wafer attach with metal studs. The flip-chip technique uses a Cu pillar for the contacts. Full integration is based on a Cu-Cu interconnection architecture.
Some remaining challenges are to indentify how to specify functions. Manufacturing needs to define preferences for back-end or front-end flows in a heterogeneous process. The good thing is that the TSVs are short, only a few µ thick, so the aspect ratios are not unwieldy. Now, all of the basic building blocks and technologies are available, so the industry needs design tools, phonic PDKs, and electro-optical models for systems integration.