Wednesday, March 22nd, 2017

Common Platform R&D Pipeline


 March 14, 2012, Common Platform Technology Forum, Santa Clara, CA—Juga Jagamather from IBM moderated a panel focused on future semiconductor innovations. The panel members were Michael Liehr from College of Nanoscale Science and Engineering, Simon Segars from ARM, Subi Kargen from Global Foundries, TC Chen from IBM, and Dongwon Kim from Samsung.

Low power?
Chen noted that scaling is ending but is still viable for 20 nm, which is starting prototypes. 14 nm is coming up, but it and the next three smaller generations depend upon breakthroughs. The power density limits prevent frequency scaling, but increased transistor density is still possible, because the energy per operation is less by 30-40 percent.

Power density limits frequency scaling but the real issue is the increasing costs of manufacture versus the increased performance. Going forward three generations requires increasing the shrink per generation to maintain the performance improvement ratios. New technology in development and changing from silicon transistors will not be easy.

Some candidate technologies are silicon nanowires, III-V devices, and carbon nanotubes. The tube technologies need work on purity and placement integration into a manufacturing flow. Carbon nanotubes are already considered well proven, but there are still many difficulties with the materials and processes. III-V materials also have a long history, but are still considered niche.

The next change will not be transistors, but instead will focus on 3-D TSV to continue to get increases in transistor density. This change will require architectural changes to consider moving computation to the data, rather than moving the data to the processor.

Photonics will not only be I/O, but also for on-chip data transfers. New memory algorithms will change the nature of caches and memory hierarchies. Using multiple cores makes the memory-core transfers bandwidth limited, so new types of memory will be needed.

Liehr summarized the work and facilities at the various educational sites in New York, and noted their efforts to incorporate industrial concerns and ecosystems into their curriculum.

Multiple fabs?
Kargen stated that the value proposition of multiple fabs is to get access to the global talent and provide geological diversification for their customers. The Albany facility has a critical mass of talent to move the R&D into production. In some ways, the Albany fab is an extension of the Malta site and both are involved in bringing up 20 nm.

Product challenges and advantages of Common Platform?
Segars suggested that the Common Platform illustrates the benefits of a disaggregated industry. The various companies can balance standards against the inefficiencies in those standards. The users need to understand the next generation processes to match their design schedules to production release. At the same time, the designers need to get more early information on models and design rules to optimize the designs.

Kim noted that some IBM people are in Samsung, and IBM is the major developer of the basic platform technology. All of the partners are starting to share more of their research, because Samsung is changing its focus from memory to SoCs with combined logic and memory. The sharing of experience and technology helps to advance the technology.

Tools and design integration?
Segars responded that ARM is not only in phones. They also are in many other types of processor-based SoCs where a high-performance, low power CPU is needed. There are a range of implementations based on tier standard platform including PCs and servers. Last year, over 40 percent of their design wins were for non-phone applications and new systems architectures.

Windows 8 on ARM?
Segars said it is getting there.
Kargen concurred that the technology point of view only requires the CPU to push performance to 2.5 GHz to be of similar performance to an X86.

Low power is key, is high performance just a niche?
Kargen observed that CPUs and GPUs are still the drivers for technology improvements, and will continue to be the key in the future. The real issue is to find the sweet spot that can be developed within a 2 year window. The sweet spot moves up and down depending upon the designer's needs. Designs in the 20 nm process are using all types of transistors within a single design.

Process development challenges?
Chen mentioned that the next generations will require major changes in infrastructure and materials. The next generation always has harder challenges than the last one did, and now the difficulties extend to the tools. For example, copper interconnect development started in '84 and reached production in '97. High-k, metal gate work started in '96 and took a long time to implement. The research included the evaluation of many elements for appropriate chemical, mechanical, and electrical characteristics.

Direct cell assembly started in '00 to consider the alternatives to multiple exposures. The economic issues cannot be ignored and the work on exposures and lithography are trying to get to a single exposure process. This effort is expected to take about 10-15 years to become a commercial reality. New elements create new challenges. The path from research to development and eventually to manufacturing requires partners and sharing of information with those partners. One new aspect is the embedded people from partners at IBM.

Historically, they have always found ways to break the barriers to the next generation process. Now the efforts have to combine many technologies including lithography, design, and direct assembly. For example, OPC has moved to mask-source optimization, but the latest versions are still moving into manufacturing. The pipeline is still full of new functions.

Liehr said that everything is part of an ecosystem. There are a variety of interactions with vendors, foundries, and development partners to provide an ecosystem for collaboration.

Move into manufacturing?
Kim acknowledged that there are many challenges to full implementation. The transfer from R&D to manufacturing is always hard, because the research groups always leave gaps in manufacturability. The fabs need to know how to make something in volume. The R&D teams learn how to do something and develop the basic technology. Then the manufacturing groups have to determine the details of implementation to maximize the margins and ramp yields. Some of these issues need more attention in R&D.

Difficulties with the Common Platform?
Segars specified problems with agreements on tradeoffs, multivariate models, and general increases in complexity. The choice of power or performance is not simple. Their long experience with low power and trade optimizations have driven system-level architectural changes. It is possible to have high performance and low power in the same chip, so integrating an SoC is no longer a choice of a monolithic processor.
Kargen added that process complexity is up exponentially. They have started early engagements to identify process and design tradeoffs. The move to Fin devices offers more choices in devices and these multiple options still have to connect the technology with the market and growth.

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