Parasitic Extraction Below 28 nm- ISQED
March 19, 2012, ISQED, Santa Clara, CA—Cary Robertson and Rick Pier from Mentor described the challenges for extracting parasitics in designs below 28 nm. The designs need better extraction to ensure timing closure and manufacturability.
As feature sized shrink, the different parasitic elements become more significant. Transistors accounted for about 35 percent of the parasitic content at 40 nm, but have dropped to less than 28 percent at the 28 nm node. This means that the wiring capacitance, resistance, and now inductance are increasing faster as their dimensions and spacing decrease.
Modeling is more difficult in the sub 20 nm nodes because the 3-D features, like the metal aspect ratios, have more influence on performance than previous process generations. In addition, retargeting, the change of drawn features within the implementation flow, can change electrical parameters. Now the orientation of the features and local interconnect both matter to the extraction process.
High complexity structures need full 3-D extraction to be accurate enough for signoff. Internal structures like raised source and drain, and the coming FinFETs, change the device models, so the standard devices have to become a part of the extraction on gates, and other raised features. For example, the poly-metal 0 interface, diffusions, via 0 and metal 1 structures all are changing due to the changes in the gate and transistor stacks. Some have advocated parameterized source and drain models that look at the details of individual features, especially contact resistance.
Some interconnect features are affected by the double patterning. The litho-etch-litho-etch process must be used for many features that used to require only a single mask. Now, capacitance is affected by offsets and lithography. The front-end of the line effects change device models, and the back-end of the line processes cause changes that need to be fully extracted. Shifts in x-y coordinates tend to increase capacitance and now the z direction also affects the loading.
As a result, tools now must know the layer color, which polygons are associated with which mask, and work towards the least pessimistic arrangements of features. This level of detail is only required for transistor-level design, all other types of design will be non-colored. At the higher levels, the complexity will already add more corners that need simulation. We are moving to a flow where the number of corners grows out of bounds. At 20 nm, there will be 10 -13 corners just for the interconnect!
The accuracy needed will necessitate many more simulation runs. At 28 nm, the full spread takes 5 processes and 3 temperatures for a total of 15 runs. The larger number of devices and the large number of patterns used in interconnect increase the data volume and number of corners needed for full analysis. The accuracy of a rule-based flow is insufficient for the demanding designs. For relatively simple Manhatten routing, rule-based analysis is still ok, but the number of outliers will increase.
To address the increasing complexities, designers will need an integrated flow that can perform a full chip parasitic and timing analysis in an overnight run. The accuracy requirements call for a tool per application: full chip for signoff, transistor-level tools for cells and devices, and reference-level tools for devices and patterns. The last set will come from the foundries.
To achieve sufficient accuracy, designers will need access to full process models, field solvers, and C-R-L engines. Their reference tools uses finite difference methods to trade performance and accuracy. They take GDS-II as an input and get 35 times the throughput of Rafael at an accuracy loss of 5 percent. Standard tools can be used for faster turn-around times at a much greater loss of accuracy.
To address the growing corner issue, they have seen less than 1 percent increase in runtime per corner with an integrated flow. By taking data from the place and route flow and extracting on-the-fly, they can reduce overall runtimes. Incremental extraction and increased integration with other tools helps significantly. As on-chip speed continue to increase, the impact of inductance will only make the extraction and analysis more difficult.
The next generation process will lead to new features and some of those features will raise new issues. Tools will need to have more automation to switch from a rules-based flow to a field solver as appropriate.