UCB’s Hu Discusses Multi-Gate Transistors
April 26, 2012, GSA Silicon Summit, Mountain View, CA—Chenming Hu from UC Berkeley talked bout the revolutionary scope of multi-gate transistors. He addressed the challenges of cost, speed, and power in the next generation of devices.
The biggest issue for many designs is to reduce all facets of power consumption. Scaling is at the heart of power and speed, but economics and lowest costs are not necessarily. The actual metric is a value-cost balance. MOSFETs are increasingly limited by scaling and the reduction in voltage.
Smaller sizes are causing size and dopant variations, increased leakage, and worsening I/V characteristics, especially at very low gate-source voltages. These limits drive higher Vdd, power, and design costs. Now, the transistors are not delivering sub-threshold gain at small sizes.
In the ideal MOSFET, there is a potential barrier from source to channel, and another one from channel to drain. Applying a voltage to the gate changes the barrier height, providing a 63 mv/decade increase in current. Due to the parasitic body capacitances—related to doping, depletion region, etc—the actual values are 70-100 mV/decade.
Thin depletion layers in actual devices create additional parasitic elements. The combination of drain barrier and short channel leads to the MOSFET becoming a resistor. At small lengths, the capacitance at the drain makes the drain into another gate. Scaling the gate oxide does not help with the leakage current paths that are far from the gate.
A solution is to make a very thin body and control the current with multiple gates, the FINFET. The key to the control is the thinness of the body. In '99, an experimental 30 nm FIN delivered 66 mV/decade with an undoped body to eliminate dopant fluctuations. The transistor operated between 0.5 and 1.05 V with no changes in threshold voltage. The device was relatively immune to thickness variations and engendered a new scaling rule.
The new rule is that fin thickness is less than the gate length to suppress leakage. Gate lengths down to 3 nm have been demonstrated. Other developments included thin oxide on fin top in '02, and FINFET on bulk in '03. These modifications make it easier to manufacture the devices and reduce the cost of the substrates. This set of changes makes it possible to use the same process for bulk and FIN structures.
An alternate structure for transistors is to use an ultra-thin body SOI structure. With a 8nm thick body, leakage is 1e-06 at 0 gate voltage, dropping to 1e-8 at 6 nm, and to 1e-10 for a body thickness of 4 nm. These findings show that body thickness is the controlling factor for leakage, and the different architectures have different metrics of worth. A fin has to have a body thickness less than the gate length, and the UTB-SOI has to have a thickness less than 1/3 of the gate length.
The drivers for the different technologies are investments. The FIN requires investment by the fabs and has a higher Ion, while the UTB-SOI needs investment from the SOI suppliers and has a good back-gate bias option. There is no clear winner for either technology. Intel has started using FINs in their 22 nm process and the foundries are planning to go to FIN at the 14 nm node. ST is using UTB-SOI at 28 nm and plans to scale to 20 and beyond. The competition will drive both technologies to become better.