June 2012 - In a discussion with SOITEC, they discussed thier new 28nm and smaller process offering on 300mm wafers. These larger wafers are in addition to their existing 200mm lines and large geometry processes that were migrated to 300mm in the past. The process offering is targeting designs using fully depleted devices and was designed in collaboration with IMEC, IBM and Sematech to address EOL processes that still have active designs.

The process offering is in two bins FD2D and FD3D. The FD2D is a Fully Depleted 2D device that is based on planar CMOS transitors. This process uses a planar deposited top layer of Si over the insulator base which eliminates the need for implanting the silicon to make the device. In this process a 25nm device yields the performance of an effective channel length of 15nm. This structure allows designs to provide the same performance while reducing the power supply voltage by 200mV.

The FD3D is a Fully Depleted 3D process that uses FinFET vertical devices on a Insulator base. The process results in a reduced variability of the Fin height and thus the performance variability of the devices.

The net results of these two processes is a 40% improvement in performance, in the commercial operating range, under static operating conditions. Alternatively, the devices can reduce power for same performance. All the device, due to their SOI construction, can support both a 10-25% overdrive capability and a complete (zero leakage) shut-off state without damaging devices or reliability.

The new processes, which have shipped over 10,000 wafers to date, have a top layer Si thickness control of 5Å variation over a 300mm wafer. The processes are using current generation imaging techniques and have not as yet moved to EUV based flows and tools. It is anticipated that thse devices will be able to perform in designs with as low as 0.6v for future mobile and power conscious designs.