July 11, 2012, FlexTech Alliance, San Francisco—Shelby Nelson from Eastman Kodak described ongoing experiments with equipment, materials, and process design to create vertical thin-film transistors. Their work is based on a variant of atomic layer deposition that reduces the influence of lithography on device geometries.
Their work in ALD has given rise to a spatial ALD. The precursor gases are maintained in chambers at a steady-state, and the important trick is to keep the precursor materials separate. One benefit of this approach is that reducing the spacing to the substrate increases the deposition rate. The resulting gas bearings enable minimum spacing of 30 microns, and the substrate becomes the chamber cover.
Eliminating the vacuum step between precursor gases allows for open air operation and eventual conversion to a continuous flow. A chamber based ALD has a first time of between 0.5 and 10 seconds, and a total cycle time per layer of over 20 seconds. In comparison, spatial ALD requires about 0.2 seconds per cycle with a precursor pulse of about 50 µs.
These numbers translate into significant throughput improvements. A typical TFT requires about 700 cycles or between two and four minutes on their equipment. In comparison, a chamber based flow would take over 4 hours with a 10 second purge time. Another benefit of this increased throughput is that material properties like sheet resistance can be varied by exposure time and application temperature rather than changing the number of layers.
The interesting modification is to turn the planar transistor on edge and make a vertical TFT. The resulting device has the gate thickness equal to the gate length, and offers interesting characteristics. To make the devices, they create a reentrant profile on the surface. The conformal coating of the Al3O2 gate oxide on the ZnO semiconductor follows the recessed surface. When the source and drain are metalized, the "shadow" of the edge separates the source and drain and forms the active vertical device.
This configuration has very high tolerance for misalignment, since the gate is always between the source and drain contacts, and is of known length. Electrical characteristics offer high currents at 2 V for a gate length of 0.5 micron. There is very low threshold variation across various channel widths, and of course the length varies with the width. So far the individual device yields are in the mid 90 percent range, so the process seems to be relatively amenable to a high-speed production flow.
The device characteristics are better for the vertical devices compared to those of a planar device, because the sub-threshold slope is steeper. In addition, the process gives two transistors per feature, since the gates are deposited on both sides of the step.
The next steps are to moving the process to a kapton base with no carrier. Equipment modifications include a vacuum hold-down to keep the substrate materials in place. So far the device yields are about 50 percent, but this seems to be at least partially a probe issue, the substrate moves when the devices are under test.
The development of vertical devices offers low voltage, high current transistors and high aperture ratios. The process is simpler than the equivalent planar process and is alignment friendly. The use of vertical features also means that there is no need for small gap printing, eliminating the need for photolithographic resolution imaging for the smallest features.