July 2012 - In a recent press tour we had a chance to meet with new Exar CEO Lou DiNardo at the company’s bay area headquarters. After time most recently at Xicor and Intersil, he is taking on the challenge of turning around the 40 year old semiconductor company. The company has over 4,000 parts in thier product lines, and service over 14,000 customers worldwide, with 42% of those customers being direct, and the balance through resellers and distributors.

The turnaround which started in Jan of this year, when Mr Denardo came on board, has focused on selling off their wafer fab and test facilities and moving to a fabless manufacturing model, as well as a 40% headcount reduction to date. These changes are now being reflected in their product mix where they are EOLing several product lines, and enhancing their high profitability and volume parts.

A focus for the prior management was the SONET and OTN Communications marketplace. These parts are being either EOL’d or licensed out as the cost of the development and die cost were not in line with the market growth and penetration capabilities of late market entry products. Gone also are the disk drive control modules for read heads, and servo control. The reduction of vendors in the marketpalce has completely eroded the price point for these products.

The new areas of focus are targeting the mobile and server markets. These include theier over 30 year experience base in power regulator and smart power management control chips. These product are not only used in mobile end point devices, but most require multiple units to support a single handset or tablet. Going along with these power management chips, is data connectivity. These chips have a heavy software aspect and are being used as traditional UART style interface parts as well as high end data connections with compression and security engines. These parts are also being kitted to support new Hadoop applications with high IOP throughput. These parts are being made available in a plug-in reference design card that is a state machine based design for the enterprise market that increased computation IOPs by as much as 12000x, and storage IOPs by as much as 120x through the use of compression.

The company is focusing not only on their products, but also a way to reduce the standard analog development cycle. The current flow is 120 days for standard product definition, 180-270 days for build and test and then about 180 days to secure a design win. They are looking for a 20-25% reduction in overall schedule through enhanced support on the design win cycle, and reduction in the build and test phase. At this time the company has returned to profitability.