August 21, 2012, Flash Memory Summit, Santa Clara, CA—We talked with Shaun Kung from Marvell about their latest memory platforms, called DragonFly. The storage division of Marvell makes turn-key adapters, controllers, and bridges for high-performance memory systems.

The new board addresses three main functions; non-volatile RAM, non-volatile cache in front of SSD RAID, and as a non-volatile SSD accelerator. They achieve these functions with their proprietary SoC, a NAND controller, SLC NAND flash, and super caps holding up the supply for DRAM in an so DIMM. The interfaces help to reduce latency, especially for small block reads and writes.

As a NVRAM, the boards addresses the amount of control that users want and need. The board supplies a low latency, large size cache front end for the storage arrays. This is helpful when the system suffers a power outage, as the NV RAM uses the super caps to hold up the supply until the data are stable and the transaction is complete. The board can handle bursts of up to 3200 MB/sec with a worst-case latency of 22 ?Sec and an average of less than 10 ?Sec.

As a NV Cache, the boards can accelerate an SSD array of up to 1.5 TB per board, and more boards can be cascaded. The combination of SSD and large cache shows a consistent improvement in I/O performance, especially with SSDs with a lot of hours on them. The cache offers the system a set of clean buffers. It also improves SSD lifetimes, by batching data for full sequential writes, rather than the random ones typical of high-rate transactions. The cache is large enough to fill full blocks at a time.

The third version allows part of the board to be both a NV cache for the storage arrays as well as read and write cache for the system. It also can be the backing store for the SSDs. The read/write cache functions provides some data protection and integrity plus the cache controller helps to maintain cache coherence. It is used as a sync mirror in a peer-to-peer structure on a back node that can migrate across virtual machines.

The integrated controller helps to eliminate storage I/O bottlenecks in both shared storage and server-based local storage architectures. Based upon industry standard PCIe adapters, DragonFly fits into commercially available rack-mount servers. The subsystem requires only a very thin kernel driver, which allows for use in any OS and hypervisors, resulting in low usage of the host server resources.

The interface is optimized for smaller size transaction database work, and other big data functions are now the primary focus. The latency and throughput are well suited for big data performance and the scalable storage can address the growing number and size of data files in distributed processing and analytics.

In other technologies, Marvell is demonstrating an ARM SSD Server Design. Their server reference design provides solutions including networking, application processors, storage connectivity and NAND flash controllers. The servers are based on their quad core ARM-based ARMADA XP SoC products. These processors are designed for enterprise-class cloud computing applications to drive higher CPU utilization and offer demand based scaling.

They also have a set of SSD-enabling Storage SoCs. They will show storage chips used in various PCIe, SAS, and Thunderbolt-based SSDs. Examples of bridge-based PCIe SSDs include a PCIe 2.0 x8 to 8x 6Gb/s SAS/SATA I/O controller, and a PCIe 2.0 x2 to 4x 6Gb/s SATA I/O controller. Thunderbolt-powered SSDs leverage a combination of an Intel Thunderbolt controller with a Marvell PCIe-SATA I/O controller.

They acknowledge that the storage area is in need of some changes. They have 72 to 128 bits of ECC protection in their SSD controller, and agree that the base storage devices are fairly good at keeping data intact. The problems occur in transit, and the various interfaces are not primarily storage transfer interfaces, but general purpose interfaces. The challenge is to incorporate some type of error detection or checking into a high-speed data flow without adding latency or excessive power. The ability to encrypt data on the fly is difficult, and error checking is even harder.