PCI-SIG Releases Latest Updates, Mobile PCIe
June 25, 2013, PCI-SIG Developers' Forum, Santa Clara, CA—The PCI special interest group is evolving their specifications to include more functions and interface modes. Al Yanes and Ramin Nechati from the PCI-SIG described the new features and specifications for PCI.
The main technology is based on PCIe, and with the increasing focus on mobile, created a mobile PCIe that uses the M-PHY from the MIPI alliance and a transactor layer for a low power implementation. The new specification allows for native OS support, eliminating the need for drivers and other software. The current M-PHY has three speed ranges, called gears. Gear one is 1.25-1.45 Gbps, gear 2 is 2.5-2.9 Gbps, and gear 3 is 5.0-5.8 Gbps.
The PCIe interface is architected for portable devices and the addition of the M-PHY and some basic link semantics will improve interoperability and allow interface to many other functions like normal I/O, storage through UFS, peripheral communications, and networking. The M-PCI-e has a new specification that is now available on-line for review.
The current M-PCIe specification does not have electrical test specifications for the M-PHY, but the interface is a high-frequency, low-power, differential physical layer that is optimized for display, camera, audio, video, power management and communications. A BURST mode allows for scalable speeds and selectable slew rates and amplitude reduce EMI/RFI with low error rates.
The M-PHY currently supports or will support the following MIPI Specifications: DigRF v4, CSI-3, DSI-2, Uniport-M (UniPro1.4 and LLI). By special agreement with JEDEC, JC-64.1 Universal Flash Storage (UFS) will use the M-PHY physical layer and MIPI’s UniPro Specification. Most recently, on June 20th, 2012, MIPI and the USB 3.0 Promoter Group announced the availability of the SuperSpeed Inter-Chip (SSIC) specification. SSIC utilizes the MIPI M-PHYSM physical layer with the SuperSpeed USB protocol and software layers to achieve high speeds and low power.
The M.2 specification is designed as a tunable I/O technology and provides a natural transition from the Mini Card and Half Mini Card to a smaller form factor in both size and volume. The new form factor is targeted for Ultrabooks, tablets, and eventually smart phones. The M.2 specification is currently at revision 0.7a and is anticipated to be released in Q4 2013.
The M-PCIe specification is now available on the PCI-SIG website. Implementers of M-PCIe technology must be members of both PCI-SIG and MIPI Alliance in order to leverage member benefits, including access to licensing rights and specification evolutions.
They also added a new cable specification for I/O expansion. The OCulink is defined as a small cable form factor optimized for internal and external enclosure usage. Basic performance is starting at 8Gbps with headroom to scale higher. They are developing copper and optical cables with emphasis on low cost of implementation. This server-centric is proposed to have a reach of 1-3 meters.
The cable uses an independent reference clock with SSC technology, and can support one external and one internal connector support up to four PCIe lanes, with all cables supporting 8GT/s. total transfer rate can be up to 32 Gbps in each direction within a four lane configuration.
For internal usage, the cables can access PCIe-attached storage, and for external use such as PCIe I/O expansion and external PCIe-attached storage. The cable spec is targeted for product adoption in 1H 2014, and is currently under development as Rev 0.7
They released version 3.1 of the PCIe spec which consolidates a number of functions and protocol extensions that were released as interim specs. The L1 power management substrates with CLKREG# and greatly reduces standby power. There is enhanced downstream port containment, and lightweight notifications. Precision time measurements, separate Refclk and independent SSC as well as process address space ID are moved into the latest revision. The final release is later this year.
Version 4.0 of the spec will double the bandwidth of the PCI-e devices to 16 GT/s. This and other changes will be released in Q1 of '15. The 4.0 spec is targeted for server apps that are operating with 40Gb and 100Gb Ethernet and with high-speed storage in SAS, etc. The spec will call for back-compatibility at the connector level.