August 8, 2011, Hot Chips 23, Stanford, CA—Richard Kessler described a MIPS-based multi-core processor that raises the bar for performance/$/Watt. This chip is focused on networking and wireless server functions and has an integrated security engine for cryptographic operation acceleration. It is designed to take advantage of packet and flow parallelism and exhibits linear performance [...]

 May 4, 2011, Multicore Expo, San Jose, CA—We talked to the Adapteva people about their high core-count, floating-point microprocessor. This chip is programmable in C using standard development tools like GCC and eclipse. An experimental test chip with this architecture had one thousand processors on the chip. The basic microprocessor is based on a new [...]