Thursday, March 23rd, 2017

August 16, 2016, San Francisco—Al Yanes from the PCI-SIG provided an update on the organization its core standards. Although no new capabilities are ready for release, the underlying technologies and standards are showing robust growth. The organization continues to grow with over 730 member companies now involved. The primary focus is on creating specifications and [...]

 February 2015 – At the ISSCC conference in San Francisco, AMD presented their latest APU architecture on their new processor codename “Carrizo”. The Accelerated Processing Unit (APU)is designed for notebooks and low-power desktop designs and features an advanced power management technology. It is expected that the Carrizo to reduce the power consumed by the new [...]

April 29, 2014, Ethernet Technology Summit, Santa Clara, CA—Joel Goergen from Cisco discussed the drives for increasing the data rates for next generation Ethernet systems. The ongoing trends have to be balanced with the constraints of physics and economics to be viable. System interconnect has moved from 20 Mbps in a 2kW chassis to 25 [...]

January 29, 2014, DesignCon, Santa Clara, CA—Perry Keller from Agilent and the chair of the JEDEC JC 40.5 committee talked about the market and technology drivers facing memories. The industry can expect ongoing turmoil and change over time. Memories are appearing in more applications, leading to consumer expectations for greater performance at lower cost. This [...]

February 18, 2013, ISSCC, San Francisco—Session 11 reviewed some of the emerging and wireless technologies. Contributors were MIT, Tohoku University and NEC in Japan, Fraunhofer from Germany, CSEM and Micro Crystal from Switzerland, VTT from Finland, ST Microelectronics from Italy, Aalto University form Finland, Keio University form Japan, KAIST and Samsung from Korea, and Masdar [...]

 July 11, 2011, IMEC technology Forum, San Francisco—Eric Beyne, scientific director advanced packaging at IMEC addressed exploiting the 3rd dimension. Planar technologies and SoCs are running into a wall. The smart phone is the biggest driver for advanced packaging developments. Users want lower power (or equivalently longer battery life) while the designers try to cram [...]

 December 8, 2010, 3-D Architectures for Semiconductor Integration and Packaging conference, Burlingame, CA—the first talk on 3-D directions came from IBM. Subramanian Iyer, fellow from IBM who discussed ” 3D Integration for High Performance System Applications”. Despite advances in scaling, materials, and silicon engineering, the IC performance levels are not improving at historical rates. Now, [...]

 November 16, Santa Clara, CA – the San Francisco Bay Area chapter of the IEEE Nanotechnology Council had their annual Q4 event at the National Semiconductor conference center. While the initial speakers were discussing manufacturing and lithography issues for sub 28nm processes, Steve Teig from Tabula, Inc gave a perspect from the design and architecture [...]