Sunday, August 2nd, 2015

June 23, 2015, PCI-SIG Dev-Con, Santa Clara, CA—Al Yanes and Ramin Neshati updated the status of the latest revisions to the PCI specifications. The organization continues to work on low power and alternate form factors for their interface specifications. The PCI-SIG defines I/O bus specs and form factors with emphasis on compliance and interoperability. The [...]

June 2, 2015, Society for Information Display Symposium, San Jose, CA—Robert Li Kam Wa from Rice University talked about rethinking the imaging pipeline for energy-efficient, privacy-preserving continuous mobile vision. The always-on world has been adding more and higher resolution imaging capabilities, so the industry has to consider how to protect the information. The primary changes [...]

May 21, 2015, Imagination Summit, Santa Clara, CA—Eran Eshed from Altair presented talking points about cellular infrastructure for the IoT. The greatest challenges are in overcoming the perceptions that LTE is a high-power, high-performance data transport technology that is very expensive. New technology developments and the latest revision to the LTE standards enable the cellular [...]

February 25, 2015, ISSCC, San Francisco—Ingrid Verbauwhede from Katholieke Universiteit in Belgium talked about the need for different design approaches and device libraries to address security challenges in the IoT. The growing numbers and types of attack vectors call for changes in design methodologies to take advantage of Moore’s law. The growth of the IoT [...]

February 24, 2015, ISSCC, San Francisco—Hiroki Noguchi from Toshiba highlighted their work on a 3.3 ns embedded STT-MRAM. The design uses a physically eliminated read-disturb scheme and a normally off architecture. Spin-torque transistor magnetic RAM development continues with efforts to overcome some key critical issues. The growth of last-level cache is helping to overcome the [...]

February 24, 2015, ISSCC, San Francisco—Mario Sako from Toshiba described a low-power 64 Gb MLC NAND flash memory in15 nm CMOS. The design addresses the performance saturation of NAND and the growing volume of NAND systems like eMMC, SSD, etc. which need much lower power to improve throughput with greater chip parallelism. The system-level techniques [...]

February 23, 2015, ISSCC, San Francisco—Jaehyuk Choi from Samsung Advanced Institute of Technology described a low-power, 15 fps image sensor for always-on mobile and wearable devices. The ability to run on minimal power opens many new applications for smart sensors beyond taking pictures on a mobile device. This image sensor has two operating modes; ultra-low [...]

February 23, 2015, ISSCC, San Francisco—Jong Mi Lee from Postech in Korea described another possible architecture for ultra-low power reference circuits. The design addresses some of the challenges of other architectures. A CMOS reference uses the threshold voltage as a reference, and is process dependent compared to a bandgap reference which uses Eg, a more [...]

February 23, 2015, ISSCC, San Francisco—Kinam Kim from Samsung Electronics gave the first plenary talk relating developments in silicon technologies and the solutions they may provide for our data-driven lines. The developments include silicon, packaging, and small chip security for IoT. The number of connected devices already exceeds the number of people, and will continue [...]

December 15, 2014, International Electron Devices Meeting, San Francisco—John Palmour from Cree talked about the state of the industry in the silicon carbide power area. The various developments in technologies allows these power devices to address more applications. Silicon carbide is being adapted for many applications, such as GaN on SiC substrates for LEDs, and [...]