February 18, 2013, ISSCC, San Francisco—Session 6 demonstrated emerging medical and sensor technologies. Contributors included KAIST in Korea, Masdar Institute of Science and Technology in UAE, National Chiao Tung Universtiy and China Medical University and ASE in Taiwan, University of Tokyo in Japan, EDA-LITEN in France, Eindhoven University of Technology in The Netherlands, ST Microelectroincs [...]
July 2012 – The Hybrid Memory Cube Consortium has made substantial progress in the past year since its launch. The advanced memory architecture solution has now completed and locked the 10 member companies of the core development team as of the end of May 2012. They have also finalized agreements with 35 adopter companies and [...]
At the 2011 3-D Architectures for Semiconductor Integration and Packaging Conference held in San Mateo, CA this month, speaker after speaker made it pretty apparent that 3D is for real. Though there are still competing flavors of 3D, and some advocate ‘2.5D’ as a safe stepping stone, the cost and reliability of 3D are now [...]
October 25, 2011 – San Jose, CA – Xilinx introduced their new high capacity FPGA the Virtex-7 2000T. The device is single package product that is a low power replacement of multiple ASICs and ASSPs in a high performance system. The part is built with a 28nm CMOS process and uses stacked silicon technologies and [...]
HMCC logo October 2011 – Micron and Samsung are the anchor companies in a new technology consortium for a high performance memory structure. The new memory is call the HMC – Hybrid Memory Cube and is being promoted by the HMCC which is the HMC Consortium. Like other technology groups, the HMCC has both development [...]
July 11, 2011, IMEC technology Forum, San Francisco—Eric Beyne, scientific director advanced packaging at IMEC addressed exploiting the 3rd dimension. Planar technologies and SoCs are running into a wall. The smart phone is the biggest driver for advanced packaging developments. Users want lower power (or equivalently longer battery life) while the designers try to cram [...]
December 9, 2010, 3-D Architectures for Semiconductor Integration and Packaging conference, Burlingame, CA— Bob Patti, CTO at Tezzaron Semiconductor illustrated the changes in complexity when changing from wafer-level to 3-D integration. The span of interconnect densities goes from 100 to 1 million connections per square mm and may total from 1000′s to tens of millions. [...]
November 3–4, 2010, Scottsdale, AZ — This year’s annual MEMS Executive Congress broke new records for attendance as the MEMS industry strongly rebounded from two years of slight declines. This first-rate event was organized by the MEMS Industry Group — which aims to strengthen the MEMS industry and market by cultivating a neutral forum for [...]
In order to address the growing need for computing and electronic processing in portable and high functionality design, TSMC, the worlds largest independent semiconductor manufacturing foundry, released their reference flow 11 for 28nm/22nm processes. The technology driver for these processes has shifted from the historic memory designs, and then processors, to the current System-On-a-Chip (SOC) [...]
