3-D IC panel – CICC
September 20, 2011, CICC, San Jose, CA—A panel moderated by Rao Tummala from Georgia Tech considered the issue of MCMs (multi-chip-modules) possibly delaying 3-D IC developments. Heterogeneous integration techniques of multiple ICs like SIP, wire-bonded stacked die, and silicon carriers offer an alternative to 3-D ICs with TSVs.
Tummala noted that MCM technology is over 30 years old and is functionally the equivalent to 2.5-D interposers. These technologies ask the question of package or IC integration, or 3-D ICs with TSVs versus 3-D plus 2.5-D interposers. Alternate packaging started with stacked TSOP (thin SO package) in '70, followed by MCMs (multi-chip modules) from IBM in '82. 10 years ago, chip stacks connected by wire bonding appeared in '00 and POP (package on package) in '05. TSVs appeared to become viable in this decade.
The advantages for all of these packaging technologies; 3-D with TSV, multiple die on interposers, or multi-package levels of integration include design efficiency, improved yield versus SoCs, analog optimization and reuse, increased bandwidth, reduced interconnect, and lower active power. The challenges include availability of design tools for non-planar work. Specifically, issues for TSVs include thermal, test, extendibility, and a need for new manufacturing infrastructure.
The key element is cost. The components of cost include the intrinsic cost of the technology, throughput and yield, and most importantly, the volume applications to justify al of the other changes. The change to TSVs is going to be more difficult than the one to flip chip, which took over 20 years to get into volume. Xilinx is the first mover into production 2.5-D products. Many agencies, companies, and universities are researching the issues today.
Toshio Kurihara from IBM suggested that MCMs will not slow the progress of 3-D. These technologies are already in production, are scalable and expandable for raw applications. The industry has critical needs for thermal, design, and test solutions, otherwise the technology will be limited to mobile applications. The availability of multiple technologies within a single package entails a change in design philosophies to take advantage of the strengths of the various technologies. An example might be a CPU with 1 GB of cache and a TB of RAM, all encompassed in a 16 chip stack.
The most practical method to manufacture 3-D ICs is to use a wafer-to-wafer stack with designed-in defect management for yield control. Without the wafer-to-wafer flow, manufacturing throughput is too low to be viable. The value of 3-D is higher performance and lower power than the equivalent SoC, which has to address long internal paths and large numbers of repeaters.
Pol Marchal from IMEC claims that 3-D is the ultimate package configuration. For example, the parts in an iPhone are about 2 mm thick. By going to a 3-d, TSV approach, a 3 die stack plus interposer would be only 0.5 mm thick. This packaging would allow the iPhone to have more space for batteries, or get even thinner than it is today.
The biggest problem is yield and cost. A thinned wafer is about 50 µ thick and causing up to 50 percent performance change on the chips due to flexing. In addition, the die stacks have a materials mismatch which will add to the stresses on the dice. The wafers have lower planarity and issues with thermal coefficient of expansion from the bonding materials. As a result, the stack cannot have any plastics nor laminates.
The technology works because some products are in production. This scalable technology allows heterogeneous processes and functions to be included in a single package. The challenges include the 3-D supply chain and business model to help determine who is responsible for integration and yield failures. One issue that needs attention is that the interposers are not testable, because they have to be tested on both sides at once.
Robert Patti from Tezzaron Semiconductor noted that they have over 40 configurations in production today. Their process permits 2-4 layers. The top layer is bonded, then thinned to 12 µ. The TSVs are tungsten and not copper. The interposer TSVs are at a 10 µ pitch compared to a 0.85 µ pitch on the DRAM. The pitch is the biggest issue, so they are experimenting with part of the memory stack as an interposer. The technology may lead to manufacturers not testing at all. The architecture allows improved repair capabilities, so spare functions from other layers are available to replace a bad section.
Rajendra Pendse from STATSChipPAC observed the high reliability of 3-D ICs. Some can be qualified for space-class operations because it eliminates the wire to wire or pad connections. The difficulties include sourcing and via manufacturing where the TSVs are 2-5µm in a 20 to 50µm thick wafer. Wire-free construction in a die-on-die configuration can used burned-in wafers.
The alternative of POP with wire bonds is not as good as wire-free die-on-die using standard dice from a known-good source. The existing applications include pacemakers, FPGA plus DRAM, and battery and silicon capacitors. The biggest problems are in getting good TSVs, managing yield, and improving pick-and-place throughput.
John Osenbach from LSI Company stated that the technology of choice will depend upon the application and the performance-cost tradeoffs. The benefits of 3-D are all well known, so the driver is the total time to market. Tests have shown that multiple dice are faster and lower total power than an SoC. The industry needs tools to analyze the full architecture to get optimal partitioning of all functions and figure out how to slice a 2-D concept into a 3-D structure.
Interconnect density has gone up over time. A BGA gets about 1-10 contacts per mm2, a µbump from 10-100, via last and multi-chip packages approach 1,000 and via first TSVs can get up to 106 connections per mm2. One concern is the increasing current density in the vias and the need for alternative cooling methods for high performance devices. The keys to success are IC and package co-design due to the special design for MCP, MCM, and silicon interposers. Test, modeling, and characterization all need more work to close the gaps in the supply base. Program management is important as is the up front ownership of definitions and agreements.
Christian Val from 3D Plus opined that timing matters. Users need to map their needs versus the existing and near future capabilities. Packaging evolution has gone from die on substrates (standard packaging) to die on wafers, and eventually will go to 3-D. The driving force is I/O density. As you go from die to package to PCB to connectors the I/O density drops. Therefore, users need to tier density changes within layers.
A low density is possible in a laminate substrate using a wafer-level thin film. High density I/O need TSVs to be the intermediate for GPU/CPU plus DRAM type of wafer-level integration. This change is very different from just adding more layers to a stacked die with wire bonding. The stacked packages become stacked die with TSVs. 2.5-D is traditional packaging with increased I/O density
This process needs to change to become 3-D. The transition to 3-D is a major paradigm shift in electrical performance and footprints. It need a good business case to work and will take over 3 years to become more than a niche, low power product.