03/23/10 – ISQED Lunch talk on DFT
By Tets Maniwa
March 23, 2010—ISQED conference, San Jose, CA—Anton Domic, senior vice president and general manager at Synopsys presented “Test of the Future-Some Thoughts for the Next Decade” in a lunch talk. Since the ’70’s test equipment manufacturers have gotten between 2 and 4 percent of semiconductor sales for their testers. From just after the turn of the century, this has fallen by half.
The transfer of investment from fab equipment to design tools is driven by changes in test design and DFT tools. Full functional testing has been displaced by scan, ATPG, and a shift to structural testing. Structural testing uses the fact that the internal registers in a design are converted into scan chains and very little logic is included between registers. The result is an ability to test the internal logic and not address the logical functionality. These changes in methodologies have resulted in an overall simplification in test.
In addition, the design tools have become more DFT aware. Synthesis and implementation tools now address the issues of scan compression induced congestion and scan chain injected area overhead and timing violations. Static timing analysis (STA) is linked to testing development to create delay-based testing, which can cover more of the possible faults than other test strategies. The STA-aware tools can identify the critical paths to exercise and identify the timing limits for those paths.
In design, reliability analysis can identify the power integrity issues involved in changing from operating mode to test mode by analyzing voltage drops and also can supply constraints to the ATPG tools to keep switching activity within power grid budgets across the multiple operating modes. Low power ATPG manages in-tester power use and enables the evaluation of power versus test patterns.
Scan compression can reduce the number of test vectors by a factor of up to 1000X which reduces test time and cost. Future generations of scan compression will facilitate compression optimization and reduce (test) pin counts to an ultimate limit of 1 test pin. The total constellation of DFT tools will migrate towards higher functionality to include DFM awareness and yield diagnostics to improve yield ramps. By combining the data from synthesis and implementation with the DFM analyses, manufacturers will be able to isolate, test, and track paths and vias through the ATPG test results and statistical data acquisition in test.
Through integration of the disparate point tools into a single entity, the DFT flow will change from a series of disconnected steps into a unified flow. This flow will help to reduce test development and implementation costs while improving the quality and costs of testing. Multi-core ATPG will permit the design of experiments to explore the patterns and faults sampling to identify the highest performing test patterns. In some tests, the ATPG performance is fairly linear with the number of CPUs at least through 8 cores. Optimization of the algorithms will enable virtually unlimited core scaling and will permit the evaluation of multiple parameters in one run through genetic algorithms, branch prediction, and speculative execution of possible test patterns.
Future DFT tools will take advantage of the oceans of data constantly being generated by the testing equipment. The tools must become design, manufacturing, and test aware, so any inputs from one area is immediately available to the other areas. This data interchange will force the various domain experts to become more aware of the capabilities and limitations of the other technical areas and be prepared to collaborate on common issues.
As information cycles from manufacturing to design to test and back again, users can evaluate the value of design rules. As DFT moves into manufacturing aware test and design aware test, data will facilitate the identification of failure patterns down to a specific on the chip. This data will permit the router parameters to favor the higher reliability and performing configurations and identify the library elements that have disproportionate failure histories. These capabilities will also expand the ability to use a design of experiments in a double blind testing framework to compare faults with and without recommended physical design rules.
The foreseeable increases in design complexity will force many companies to move towards 3D integration. This change will make manufacturing test more difficult and will require revolutionary changes in test development and implementation. The test hardware is getting better and on-chip test capabilities like BIST (built-in self test) and MISR (multiple input signature register) continue to improve test costs, quality, and performance. The biggest challenge will be in testing the next system-level chip, where software will become the bottleneck in final testing. The advent of new challenges will spawn new competitors and these people will invent new techniques to address the shortcomings of the incumbents.
