High-Perf DDR3 Memory Controller for CE – Rambus

 DDR3 memory is designed for low power and high performance applications in gaming and graphics systems, computing environment, mobile & tablet devices and also hdtv & consumer products. The consumer marketplace is dominated by line cord, rather than battery, powered products which support larger memory configurations and component footprints. Due to the nature of the consumer electronics market, systems cost is a driving factor.

This has resulted in the new memory controller increases performance without increasing cost. The new controller utilizes a proven wirebond technology that is $1.50/package less than previous solutions. The controller chip is assembled on a standard 4 layer board which reduces crosstalk at data rates over 1600Mbps while supporting higher memory capacities. A typical solution is shown in the accompany figure. This configuration has been tested with actual TSMC 40nm designs on 1600MTps, 1866MTps and 2133MTps (Mtps = million read/write transactions per second) designs. These DDR3 designs run proportionately at 10% of the power profile of DDR2 solutions.

Rambus DDR3 Mem controler

The solution Rambus is presenting is part of a new model. The DDR3 controller features 1.35v, 1.5v and 1.8v operating modes and a FlexPhasetm timing adjustment capability. This FlexPhase adjustment supports data, address and the clock signals.. Another key feature is the programmable control and calibration of the output impedance and the on-die termination. These controls allow for a reduced part cost in the creation of the overall consumer electronic product by eliminating external components, and insuring correct operation over the entire operating temperature range.

For incorporation with new designs, the product features an integrated DLL for ASIC interface and a high performance PLL for supporting both a synthesizable ASIC design flow and the synthesis of the device clock circuits. Unlike previous offerings, the PHY solution (physical layer implementation piece) is a full development package. It features implementation documentation for both 40nm and 65nm processes, the digital memory controller in RTL language, the design architecture and simulation/verification IP. Traditionally, these modules have been complete “hard” PHY blocks, but do to manufacturability issues at these technology nodes, a “soft” design transfer is the preferred level to release the design data.

Rambus DD3 PHY Solution

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