Programmability and Future ICs – SFBAC IEEE Nano Council
November 16, Santa Clara, CA – the San Francisco Bay Area chapter of the IEEE Nanotechnology Council had their annual Q4 event at the National Semiconductor conference center. While the initial speakers were discussing manufacturing and lithography issues for sub 28nm processes, Steve Teig from Tabula, Inc gave a perspect from the design and architecture side. The premise was that programmability was becomming a dominant feature of these deep sub-wavelength processes and had architectural impact on the design.
The reason programmability is an issue is to help address the cost of ASICs by creating platform and FPGA products. Steve compared todays IC design world to that of the software world when the dominant technology was punch cards. Under that scenario, there was no software industry per-se and large scale program development was not possible under the turnaround time restrictions of a “punch- submit to central computing – next day get a printout of results for issues you asked about a-priori to the results- determine a fix – punch new cards and repeat” loop was changed to an interactive environment. This scenario is the same as ASICs are facing, with a long development cycle and submit and wait for manufacturing and then only be able to review the results that were planned under the test coverage assigned – which still leaves long debug and revision cycles. The difference in ASICs vs software is the multi-million dollars submission cost for IC vs thousdands of dollars cost per spin for the punch card days. On the software side, the move to interactive development on a desktop, changed the whole scope and cost of development.
Similarly, for ICs the solution method for the high cost of design (now in the $100M range) is moving toward platform products that support application configuration through software rather than one-time use logic. FPGAs and memories have recently dominated the aggressive processes, as the high one-time cost can be amortized over multiple designs. A programmable device has to be able to support every netlist possible rather than an ASIC which only has to support one. This drives the FPGAs to be very area inefficient and also high power when compared to a custom design. Steve identified that 90% of an FPGAs area is interconnect and 70% of the delay is due to the interconnect. With the cost of silicon at $1B per acre, the area inefficiencies of current PFGA high performance architectures cannot continue.
Tablua has created a new architecture that is called “Spacetime” that features a significant area advantage over existing FPGAs while supporting the same benefits of programmability and high level system implementation. The technology revolves around the ability to rapidly reconfigure blocks to new functions which reduced the number of LUT blocks and the interconnect distance the signals have to cross. With the new architecture there is a 2x-4x density improvement over current designs for a given area of silicon. In addition to the density improvement, the reduction in the number of cells, increases the power performance ratings for the designs.
The challenge of interconnect is a major one for new technologies. With the ability to put billions of transistors on one design, the need to breakout signals to talk to other points is a major issue. One of the directions is to address 3D interconnects with TSVs and other in-die bonding solutions. The “Spacetime” architecture of the Tabula array, utilizes internal function registers for helping support the interconnect between fucntion blocks. As a result, it can create an effective hundreds of thousands of connect options rather that the finite hundred to thousands of connections in the multiple FPGAs on a board designs. By supporting a “vertical” style interconnection and programmability scheme, the new array acts more like a skyscraper on interconnect and content that a large spread out struction such as the pentagon.
