Common Platform IBM

 January 18, 2011, common platform technology forum, Santa Clara, CA—Gary Patton, vice president of R&D at IBM talk of a technology innovations required to move processes to 20 nm and beyond. Physical scaling is hitting a wall and it’s now costing exponentially increasing amount of money to develop the next generation processes.

Because of the costs and the physical limits, next-generation materials and processes are going to be increasingly complex. Devices will use a high K. metal gate process with strain engineering and a lot of other innovations to work. This extremely high complexity in materials and structures requires R&D with a very long-term horizon. In addition, the foundries must collaborate with their customers to ensure convergent goals.

As a result, the industry has had to develop new business models where suppliers of equipment and materials, foundry partners, and EDA companies all share in their own incremental sectors. For example, the gate stack now requires all of the suppliers to work together to optimize results, because these are now atomic-level processes. In the interconnect area, process equipment vendors must work with EDA companies and other suppliers to develop copper plate aspect ratios at 5 to 1.

R&D has to start the fundamental levels of chemistry and physics, then move to advance development where experimental devices are created. After these initial devices show promising characteristics, the semiconductor equipment manufacturers become more involved in moving the process to production status. Finally, the technology, as a combination of materials, processes, and tools used has to be moved to production.

This collaborative ecosystem, a function of their joint development agreement, includes other semiconductor manufacturers, IP, EDA, and consortium / academia in the development process. To continually increase performance and reduce individual device areas requires innovation in materials, structures, processes, and architectures. These nanotechnologies depend upon and drive changes in lithography.

Immersion lithography was developed to overcome issues with numerical aperture and now computational lithography simultaneously optimizes the light source and masks. Source masked optimization (SMO) requires pixelized light sources that are matched to mask patterns to create the high resolution images. Their work in this area has been in partnership with ASML, Zeiss, Toppan, and Mentor Graphics. At 80 nm metal pitch, they are on the threshold for single or double exposure. SMO allows them to use one exposure for two-dimensional patterns, delaying the requirement for double exposure.

When the industry gets to 14 nm, all features will require double patterning. This is expected around 2014. To get to 11 nm will require extreme UV sources to pattern the images. At 20 nm devices will still be planar, however, at 14 nm all devices must be fully depleted. The primary candidates are finFET or ETSOI (extremely thin silicon on insulator). Devices will require shallow junctions, more complex gate stacks, and extensive strain engineering for the channel mobilities. Interconnect will change to some type of nano wires and possibly longer-term to carbon nano tubes.

When they are preparing to release the first 32 nm process, they were developing high K. metal gate devices based on the gate-first metal gate process technology. As they moved from 32 nm to 28 nm, they found the latest process did not require strain engineering. When they move to the 20 nm process, they will change to a gate-last technology because of different technology demands compared to 28 nm process.

As they develop this process they are trading off simplicity versus performance and power and found the gate-last provides higher performance. In addition, as they move beyond 20 nm the gate-last process alleviates stereopsis. ETSOI remains a simple, planar process and is therefore promising, but the finFETs may be more compatible with double patterning.

The interconnect technologies are also areas for extensive research. They’re looking at silicon nano wires as well as ways to reduce the copper integration scaling issues. Higher performance will require moving to even lower K interlayer dielectrics but the challenge here is as you reduce the K factor, the materials get softer and weaker with the ultimate pay being one for a vacuum. The attacks will also extend above and through silicon as packaging requirements move towards full 3-D integration. Modeling and controlling thermal issues are a major problem.