PCI-e overview
June 22, 2011, PCI-SIG developers forum, Santa Clara, CA—Al Yanes and Ramin Neshati gave an industry-level overview of the PCI-SIG. The organization has over 800 members, many of whom are readying the release of PCI 3.0 boards and systems. 23 boards and 16 systems were submitted for evaluation at the latest workshop. The next generation of PCI-e will include graphics, Inifiniband, SSDs, 40/100G Ethernet, and PCI-e switches.
Version 4.0 is starting investigations. Speed will increase to 16G transfers per second, but some issues like cost and complexity are also on the table. The early proposals will not require any logical layer changes, but will need a new analog PHY to address functional issues like length, number of channels, power, materials and connectors. The connectors are likely to be mechanically the same, but with improved electrical characteristics. Lengths are likely to be somewhere between the medium and short version of PCI 3.0 without going to active repeaters, but historical evidence shows that people want longer lengths at speeds above 10G.
Due to the very high speeds per lane, the lanes are going to have bifurcation capabilities. The PCI-SIG is fairly certain that PCI can be extended beyond the current 3.0 limits but there are a number of issues to investigate and resolve before finalization. Investigations will commence in the second quarter, with preliminary specifications some time later. The member companies are doing the various phases of work and sharing their results and models with other in the organization. A final specification should be released in time for new 4.0 products to start appearing in about 4 years. In the mean-time, intermediate revisions to the current 3.0 specification; 3.3, 3.5, 3.7 will be released.
Like 3.0, the new specification will be able to trade lanes for speed and power. They expect to stay on copper interconnects, but will have a provision for optical in the future. The analog PHY is going to change and may have to include forward error correction or advanced active equalization. The physics issues are the first to be addressed and then whey will look at the other layers. The PHY has to scale up at a constant power. PCI will continue to be a general purpose architecture with back compatibility to previous versions.
In another area, the PCI-e cable form factor is in a workgroup. They are looking at a lower cost version with reduced width and length for the client and mobile space, with adoption likely by ’13. Future versions will look at optical for the 8G bit rate with a maximum length of 3 meters and for future scaling up to a fourfold increase in bandwidth. This is about the same interconnect space as the new Thunderbolt interface.
