Energy Efficient Electronics – UCB E3S Day 2
November 4, 2011 – Berkeley, CA – The E3S center at UC Berkeley, continued its research overview on energy efficient electronis. The second day of the conference focused on new device physics and circuits based on phenomenon other than electron movement along with new ideas for logic design.
The day opened with a presentation from Dr. Naresh Shanbhag of U of Illinois Urbana-Champaign on an alternate approach to computing. Current methods of computing are based on the concept of reliability being error correction for noise immunity for von Neumann architecture logic. Another concept of statistical probabilistic error-resilient computing has been around since early 1900’s and never really grabbed a foothold in the semiconductor community. With shrinking device sizes and reduced operating voltages, this concept of stochastic computing is becoming of interest again. The driver is the variability of the devices in sub 20nm processes (down to single digit geometries) no longer operating as the require “definitive state” of ON or OFF as a switch. This switch concept as a logic decision maker is the core of the von Neumann architectures. An overview of the way logic works, and practical circuit implementations and prototype chips done at universities and industry were presented.
The next series of talks took a different approach to low power from the new circuit topologies – they focused on new devices. North Carolina State, UC Berkeley, Stanford, LEAP, Tohoku University, and MIT presented on photonic devices, magnetic spin devices, nanoelectrochemical switches, and magnetic tunnel junction devices. These have in common the ability to move to very lower power supplies, not being limited by the transit times of electrons through standard metals, and having device characteristics that are not gated by lithography. These devices are leading candidates for future, typically 10+ years out, technologies to take over from the current Moores Law trail.
The day concluded with two side topic presentations – Jan Rabaey discussed implantable electronics for human enhancement. These include both sensors and probes for detecting brain and nerve activities as well as pro-active devices that can re-introduce signals to those areas. The challenge is power per unit area and the effective location EM radiation that results. As these are living systems, the radation and power exposure needs to be minimized, however that power program is contrary to delivering th ehighest operating power to the electronics and getting maximum data back. The directions being investigated include the RFID techniques for pulsed power and antenna back modulation for data transmission.
Google presented a high level, where devices are ants – they talked about the view from an airplane, on data centers and data center power. Their first revelation to the audience is the lower power electronics for compute and servers do not lower the power requirements of the data center. The planning for a data center includes land use, roads, water availability, power, air temp and air patterns, weather, building construction, and available personnel in addition to the computers. In this scenario, the creation of a 30MW data center (a typical unit) has a fixed cost that far exceeds the computer resources. As the power is reduced for the individual computers, more units can be put into the same footprint, but the data center itself will always draw 30MW. The lower power in compute is the guideline for reducing the number of new data centers that have to be built to meet resource demands, however the amount of power currently being consumed will not be dropping. They are currently building data centers with a 1.12 power efficiency factor which translates to only a 12% total overhead for power between HV transmission lines and the use in data center compute racks.
For further information please visit the department web site at Center for Energy Efficient Electronics.
