Nonvolatile Memory – ISSCC2012
February 22, 2012, ISSCC, San Francisco—The need for nonvolatile data storage continues to grow with demands for greater density and higher reliability.
Toshiba presented a 19 nm, 64Gb multilevel flash. The internal architecture was completely revamped in the move to a three bit per cell structure. Internal cells which featured 16 kbit planes and all bit lines are parallel. Bit lines are split into even and odd groups others one sense cells for every two planes. This structure requires multiplexers between the even on planes, but allows all the sense amps to be on one side of the die, reducing average connection lengths. In addition to structural changes, they found it necessary to change the programming algorithm to address the cross coupling of state storing programming area programming cycles now start from least significant bits and finish with the most significant bit going through the standard program read program read cycle until the read voltage is stable. SanDisk, with Toshiba, presented a 128Gb three bit per cell NAND flash memory. This MLC memory chip claims the density record as well as fast right throughput of 18 MB per second and a read throughput of 400 Mb per second. This chip uses a similar architecture as the 64 Gb device, but is made to be packaged in an SD format card.
The University of Tokyo found ways to increase lifetime by a factor of 10 and reduce errors 76 percent in solid-state drives. The addition of a modified low-density parity check that includes a model of cell interactions and statistics results in extended data life and reduced errors. The table driven bit error rate model is also used for wear leveling and error prediction. Results at 85° C. predict much longer data retention and lower error rates.
KIAST presented in encode/decode controller for SST’s based on a BCH encoding scheme. This controller changes the host/flash interface and puts more elements in parallel. Multiplexers at the encoders allow 32 bits to be processed in parallel to reduce latency algorithmic flows change to reduce complexity and increase the search area. They still need to work on addressing the high fanout required of this architecture.
Infineon created a bit line capacitance cancellation sensing scheme to achieve 11ns read latency and maximum read throughput of 2.9 GB per second. This development is directed towards automotive applications of flash memory embedded within an SOC.
Samsung described a 533 Mb per second DDR interface on MLC NAND flash. The 64 Gb device. Like the Toshiba device, they have found that reordering the programming sequence minimizes voltage threshold changes resulting from a high-level programming on the most significant bit. The pipeline eliminate the flip-flops to reduce the latch right time compared to the settling hold and clock times. Smart algorithms in the controller find the optimal read levels, and minimize the bit error rate.
Moving to other technologies, Panasonic described a multilayered cross-point resistive RAM macro. The basic storage cell uses TaOx as any resistive memory element. Programming the memory of element requires a bidirectional current, one direction for low resistance the other, for high. Driving a current below the right threshold allows the resistance to be read, which can occur in less than 10 ns. The resistive elements require two metal connections per cell, and cells can be vertically stacked. Some issues in this architecture are the need for bidirectional switch for programming, stable switch for the cell, and the high leakage currents associated with sneak has in the array. A new bidirectional diode made of TaN/SiNx/TaN meets the switching and current requirements and fortuitously allows processing below 200° C.
Another ReRAM from National Tsing Hua University is geared towards low supply voltage mobile chips in a frequent read, seldom write application.
