Multimedia Chips balance power and HD – ISSCC2012

 February 21, 2012 – San Franciso, CA – The ISSCC conference session on multimedia chips had a focus on addressing HD needs up through UDTV (4Kx2K) and multiple codecs while also meeting a new system level lower power target.

The first paper of the session, from Samsung, discussed their new 32nm HKMG Exynos quad core ARM v7 core processor that has a 2 port DRAM controller with a high speed GPU. The Open GL ES 1.1/2.0 compatible GPU has a quad core pixel processor, a single geometry processor and its own dedicated L2 cache. The processor was designed with a data flow optimized for a hierarchied bus architeture rather than a point-to-point interconnect plan. This provides an inherently high bandwidth with a lower power requirement. The product also featured a number of design techniques to lower power (DVFS, Active Body Bias, etc) which provide some power usage benefits, but these are overrun by the power reductin from the scaling and the fact that in data processing mode, the power features cannot be utilized. In processing mode, the devices actually get higher than normal operating conditions, due to forward body bias, to meet throughput demands. The device also features DTM (Dynamic Thermal Management) which makes srue the dataflow and the data rate do not impact the BER or performance of the processor.

Two of the presentations, one from KAIST in Korea, the other Toshiba in Japan, dealt with new image and object recognition chips for identification in 720p HD video streams. The driving specs were 320mW at 342GOPS of operation for a 650GOPS/W efficiency and 749mW at 464GOPS of operation for a 620GOPS/W efficiency respectively. The area of object recognition is becoming a key task for surveillance and UAV applications. As the resolution and frame rates increase, the real time processing increased in complexity, mainly due to the amount of data to be processed and analyzed. These two chips used new internal architecture for the datapaths and caching pipelines along with improved keypoint and edge matching algorithims. Both solutions were now utilizing a distributed proessing method that supports multiple cores and threads in the same die.

The session closed with two papers on high resolution multi-codec standard chips. The key point was addressing higher data rates and pixel counts per frame, and managing the power and throughput of the processors. Waseda Univ of Japan, presented a 2Gpixel/s video decoder that is targeting the 8K HD video frame applications (FTV and 3D QHD). The chip addresses the large amount of frame data with an in core partial frame buffer as well as a new frame level parallelism than manages the dependancies between the I/P and B frames in the datapath. To address some of the I/P and P/B transistion challenges, they have created a 4 slide entropy decoder in addition to the standard data deoder. This allows for the optimal use of a L2 cache frame buffer that can manage uncompressed P & B frames and a high speed partial load of the I frame. The design also looks to slice lock on the encode path of the data stream , not on the decode side. This design method allows for processing of up to 16 HD streams for 3DTV applications.
The final paper was from TI and described their new OMAP4 application processor, now in 45nm CMOS> The multi-standard CODEC chip handles full 1080p30 and 1080p60-3D video streams along with VP8, H.264 – rv8,9,10 and MVC. For video conferencing, real time, it handles H.261, H.263, H.264 and SVC formats. The multi-stream processing is handled using a 2 macro block pipeline which helps handle the reduction of latency by de-coupling the data stream processing from the pixel processing. Traditionally, this cannot support the latency requirements of RTP without impacting the bitrate. The decoupling allows for a 10% IVA-HD power reduction and a 15% DDR bandwidth reduction for B frames resulting in an overall 30% DDR bandwidth reduction. This bandwidth reduction, in association with the process shrink, resulres in a 6x total pwoer reduction for local processing . These power reduction solutions, in addition to the architecture changes allows the OMAP4 chip to be targeted for mobile applications where content in multiple formats from over 20+ video profiles can be processed.