IBM Forecasts New Semiconductors
Scaling flattened out about 10 years ago, so the next generations of silicon will need disruptive changes to be viable. This situation is not unique. In the ’80’s, bipolar devices had problems with power consumption and needed to go to water cooling to operate. The disruptive technology that saved the day was
This technology allowed the industry to begin its long march of process scaling. Unfortunately, when the oxide thickness got to 10 Å, or about 3 layers of atoms, the scaling trends slowed down. To address the limitations, the industry introduced materials innovations like strain, high k metal gate, and other processing to continue the scaling process.
On the circuit front, the industry instituted high-performance embedded memories to eliminate external connections and traffic to data, allowing performance scaling without changing physical dimensions. The next decade will see new devices that will have minimum dimensions approaching 7 nm, and will see 3-D stacking of functional elements at the device and die/wafer levels.
As we get to the atomic dimensional limits, we will see carbon nanotubes and other devices not defined by lithography. This change will require fundamental research into materials, processes, and devices. The advanced semiconductor R&D will lead to prototypes for processes and packaging. The technologies will take a long time to develop and transfer to manufacturing, so there is a great need to perform a lot of early R&D.
The roadmap for lithography is changing. We have passed the extensions available from immersion and increases in numerical aperture, so the 22 nm node will require source-mask optimization. Computing the interactions between pixilated light sources and mask features will extend the resolution one more generation. The lithography will require additional process tricks and double, and more patterning at 14 nm. One alternative is to define prescriptive ground rules and selected exceptions for design because restrictive rules have become too complex.
EUV promises single exposure below 20 nm, but so far the EUV tools suffer from low throughput and short operating lifetimes. EUV also has to operate in a vacuum and changes the optical system to reflective optics compared to the refractive ones in use for optical. Finally, the masks have no pellicle, so defect-free masks will require new and improved inspection technologies. The work at the Albany center will start up in the second half of this year.
At the same time, they are continuing work on immersion processes. One new technique is sidewall image transfer, a self-aligned lithography process that uses a litho-etch, litho-etch unaligned process that allows self-alignment of the vias. Other technologies include block polymer directed self assembly, and phase separation at the10 nm node.
Other work in devices is examining various implementations of fully depleted transistors in extremely thin silicon on insulator and finFets. These devices address the short-channel and threshold issues and virtually eliminate leakage paths. They have found that the fins have to have rounded tops to eliminate the high voltage fields associated with sharp edges. Nano-wires in silicon and carbon, and 2-D graphene are on the long-term horizon to continue the performance scaling. Graphene devices have registered 25 GHz for RF devices and the nanotubes have operated on 0.5 V. The benefits of these alternative materials are a 10 x improvement in energy per transfer or a great increase in speed.
Some of the challenges to be overcome for the carbon structures are that currently 30 percent of the structures are metallic. Separation processes and material generation have to improve to get to fewer than 10-4 metallic devices compared to the 10-3 best case today. Another problem is the inability to scale interconnects to the same levels as the devices. The resistance is going up with scaling, but the capacitance is not going down as quickly, due to high k and the increasing aspect ratios.
Reliability is dropping at the smaller nodes due to the much smaller cross sections available. The metals have to meet a new requirement for correct profiles and the high k materials are more brittle and weaker than the older insulators. The many materials needed for the metal and insulator layers need to be engineered for better coverage and bond strength as well as being more stable in the higher electrical fields present in the smaller dimension nodes.
Expect to see more integrated photonics in the I/Os. The on-chip waveguides can multiplex many wavelengths of light at the input side and the tuned waveguides on the receive side can separate the data. Eventually, the photonics will be integrated into a 3-D structure and will even be used for on-chip communications.
Packaging has to address the problems of power and density, bandwidth, and chip-packaging interactions. The thermal issues cause the chip-package interface to have high stress over temperature cycles and the other materials in the packaging exacerbate the problems. Some of the organic materials can deform laterally with stress and therefore can reduce the stress on the flip-chip contacts. Packaging design has to change to enable systems in a package and other alternatives. The full 3-D process technologies and designs need more work on the contacts, TSVs, and cooling before they will be reliable enough for production.
