The quest for the 1 Trillion Transistor SoC

 April 12, 2012 Mentor Graphics User2User Conference, Santa Clara, CA—Sameer Halepete from Nvidia projected that super phones will become the driver for compute power rivaling that of a supercomputer. The integration of al of the functions into a single chip will be the impetus for the trillion transistor SoC.

GPUs are getting bigger and the gate count is increasing over time. Using a linear extrapolation, the growth rate indicates a trillion transistor chip within the next 10 years. The questions for the industry are does the market for such a chip exist, and will anyone be able to make the IC.

The increasing functionality and performance of GPUs and other functions in a single chip will reduce the virtual part of VR and become more real. There is wide spectrum of capabilities and performance in the mobile environment, but over time, some of the mobile devices will have the performance of a low-end supercomputer.

Mobile devices are increasing in variety, but are now dominated by phones and tablets. The mobile devices are a platform for growth, because scale matters. Some forecasts predict 1B phones will ship in ’15, which will drive all parts of the ecosystem.

The mobile platforms are becoming one of the principal platforms for gaming. The improvements in algorithms and device performance improve the capabilities for lighting and shading to produce cinema-quality images that approach realism. These capabilities are also used in cinema for off-line rendering and computer-generated images.

In professional computing, CAD on workstations started with wireframes. These images greatly improved when shading became available to the average user. Ray tracing further improved the images and now we are seeing photorealistic images that are generated by a computer and imaged with a GPU. The visual arts will not be held back by a lack of technology.

Another area for GPUs is in supercomputing. This area may be the actual first target for the 1T transistor IC, because the systems need more parallelism to get their performance. The single-threaded compute model is limited in its ability to scale to higher performance.

In fact, the performance gap between single threaded machines and GPU enabled machines is over 100x for scientific modeling. Three of the top five supercomputers are GPU powered as are 35 of the top 100 machines. Visual computing drives the performance needs across all platforms.

The chip implementations are getting harder, not because of the architectures, but due to the changing processes. The change from 40 nm to 28 nm increased the fab prototype latency by 4-6 weeks. The shrink added many additional steps to the process flow. The lag also applies to the first production shipments, but the ship date for the product doesn’t change.

Developers need to make up the time loss in some way. In charting bugs discovered and fixed over time, the rate of decrease for random testing and its many variants show that the verification methodologies are limited. Changing the verification tools to formal methods improves the verification time and completeness, but requires much more work up front. The designers have to develop properties and assertions for their circuits.

Changing the nature of timing closure also reduces total design time. The current tools put maximum effort on all paths, unless told otherwise. When the front-end designer works closely with the layout people the arbitrary and inconsequential timing arcs are identified before the layout person spends a lot of time in optimization.

The designer productivity has increased by 4 orders of magnitude over the last few decades. The number of transistors has increased even more, so the designers still need to improve productivity by a factor of 30.

The good news is that most large chips are highly replicated. Improving hierarchical analyses for timing, etc. would improve overall throughput. Most timing analysis is still brute force through static timing analysis, but this technology does not scale to the tera-transistor level. Abstract timing models don’t exist, and the few models that attempt to include hierarchy don’t match the reality on chip.

Productivity is improved by using advanced macro placement. It takes a long time to manually place macros like RAM into an SoC, because the initial floorplan usually doesn’t have any realistic timing placement. The CAD person has to make a number of trial placements and loop through timing closure to get to an initial placement that can be the primary starting point for the final place and route.

Another area for more emphasis is improving time to performance, and now performance per watt. Power budgets have not changed for awhile. The upper limit for power is between 225 and 250 W, and frequency is limited to about 1 GHz. To get better performance, designers now have to increase energy efficiency. Techniques like voltage and frequency scaling have to be considered against utilization for power management.

Designers take advantage of different threshold and supplies in their designs, but the tools are limited in their ability for detailed analysis across these varying parameters. The process of finding new areas to change for optimization is about half a manual process, and likely to miss many chances for other optimizations. To tools can do a better job of searching through all of the function blocks than a person.

A tool to analyze changes in clock gating and other power management techniques can also help in workload analysis for voltage and frequency scaling. As the frequencies continue to rise, the increased variations in devices make the timing analysis and process more closely tied together and the correlation between these two areas becomes more important.

Accurate signal coupling models make static timing analysis more accurate. One way to get better accuracy is to extract the critical paths and run them through Spice. The main issue with this flow is that the margins for the process may be much different than the simulation resolution.

After all of the engineering is completed, the design goes to fab. Here, the total area has been fairly flat over time, at about 500 mm2. however, the cost per square millimeter has increased with each process shrink. The product engineers have to improve the ramp to volume rates to help recover the increased costs per wafer.

Test cost are growing and are now about 5 percent of the total cost for a product. If the testing is linked to the design database, the product engineers can pinpoint defect locations through a combination of laser probes and ATE to reduce the defects in production.

Visual computing is driving the growth of SoC designs. The challenges for the designers is to get the design within the constraints of time, cost, and power. These challenges are the same as when the graphics accelerator industry started.