ARM Mali extends Visual Computing
June 2012 – ARM recently presented an update on their MALI GPU platform, which is targeting the estimated 4B devices utilizing graphics engines by 2016. The GPU is addressing the visual computing market with has been tasked at improving the QOE (quality of experience) of the user, while consuming digital content. The prevalence of graphics in the media distribution chain is driving the creation of integrated systems of CPU, GPU, Memory technology, and data connection fabrics. These blocks have to be assembled to provide high performance while being constrained in a restrictive size, power and thermal budget.
The current core the Mali 400 is a mainstay of the DTV industry being incorporated into high volume chipsets and products from Samsung, LG, and Mediatek. Rockchip has integated a dual M400 with a dual A9 core for the Samsung Galaxy S III which was recently brought to market. This high performance platform is being driven into a large number of OEM mobile products.
The basis of the Mali cores is an architecture that is scalable, has high density, is low power, and can be optimized in the SOC with the CPU and Memory interfaces. This provides a power performance lead for the tablet SOC space. Recently the Exynos5 process from Samsung pushes the technology edge with a dual A-15 CPU and Quad T604 graphics. These chips and cores are supported by the OpenGL programming language.
These new multi-core GPU implementations are causing a split in the graphic for display and graphics for compute marketplaces. As tablets have outpaced TVs for being the resolution driver, these multi-core solutions are needed to address the shift from 2K to 4K and higher displays. For this application the soon to be recently released Mali 450MP will support up to 8 cores while requiring no sofware modification in the applications. To supplement the display processing, the T604 (targeted for 2012), T658 (targeted for 2013) and next generation Skymir (targeted for 2014) GPU compute cores will be released.
These IP cores are designed to simplify multi-core use by providing cache coherency with a single shared memory design which minimizes the cost of off-load from the GPU. This allows compatibility with LPDDR2 and LPDDR3 systems including wide I/O up to 6Gbp-12Gbps of bandwidth. This performance level is applicable for both mobile/desktop products as well as in-cabin infotainment and safety/vision systems.
