The Impact of Emerging Memories
August 21,20-12, Flash Memory Summit, Santa Clara, CA—David Eggleston from Rambus described the affects that changing technologies have on systems. Moore’s law allows for increasing memory over time and the availability of various storage modes influences next generation systems.
Over time, systems adapt to memory. As a revolution, this leads to massive changes which amount to a barrier to change. All computing is seeing more storage, users now have up to a TB in a mobile device, and access to a PB in the cloud.
Success and survival in this environment requires the ability to improve the bit cell to scale into arrays and to change architectures, the NVM interface to handle and cover the deficiencies in subsystems, controllers, and the storage interface. Technical knowledge is required in all of these areas for effective changes.
Memory scaling is a function of an area function “f”. An SRAM has a physical limit of 100 F2, a DRAM is 6 F2, and a NAND cell is 1 F2, and can scale even more with MLC. For any emerging memory type, the smallest cell will always win. SRAM was displaced by DRAM even though the DRAM needed to be refreshed. NOR was replace by NAND but needed to add ECC to achieve endurance and reliability requirements.
Now, the issues are performance and reliability, and in some applications, write speed. A NVM is not useful if the last write takes longer than the system power takes to go below any operating thresholds. The technology has moved from consumer applications like cameras and music storage into much larger storage arrays immobile phones. These new apps require greater reliability at the system level.
The improvements in interfaces and bit integrity have allowed the basic consumer SSD to move to the enterprise with only a few enhancements. The challenges are that the bit cell performance and reliability decrease with cell area, but the SSDs need much higher numbers to be fit for enterprise use. As a result of these needs, the DSP, ECC, and RAID functions have changed to accommodate the desired specifications.
The criteria for the next generation of storage devices are the ability to scale for at least 2 process generations, and good performance and write speeds. The primary contenders include DRAM—for main memory, fast, good area at 6 F2—NAND for bulk storage, slow, and the new technologies of resistive RAM and phase change RAM.
PCRAM has an area factor of 5-10 F2 and a 10 nS write time. RRAM has an area factor of 0.25-20 F2 with a write time of 10-100 nS. NAND has an area factor of about 4.5 F2 and may be scalable down to 1. The biggest issue for the NAND devices is their write time in measured in the tens of thousands of nS. Since all of the candidates have similar area functions, the key is the write speeds.
One of the barriers for the PCRAM is the bit cell design. The latest circuits replace the transistor with a diode that can supply the needed current drive. The circuit limits current with a resistor. On top of the bit cells, is a stacked crosspoint array. This array provides interconnection to a 3-D RAM stack to improve packing density.
The array architecture and the NVM handling make the failed bit cells useable, but need knowledge of the low-level physics to be workable. On top of the hardware is a set of controls that can optimize block-, tile-, and page-level management. New algorithms and coding allow the DSP to perform advanced wear and leveling functions to improve reliability.
To use all this performance requires new interfaces that impose minimum overhead and deliver 400 GB/sec/pin over a PCIe network. Power management and other housekeeping functions will be integrated into the controller. In the more distant future, expect to see more intelligence moving into the memory. The back-end of the line will integrate logic and memory for a mesh compute structure.
The future is not that far off. Panasonic is projecting to release RRAM for embedded functions in ’14, and by ’18, the local store may totally eliminate DRAM, and NAND in favor of a new memory technology.
