Hot Chips ’12 Microprocessors
August 28, 2012, Hot Chips Symposium, Cupertino, CA—This year’s Hot Chips key topic was power management. Intel, AMD, and MIPS all talked about re-architecting the cache controller to reduce misses and, as a result, greatly reduce power. Other major changes included new logic cells and significant architectural changes in other functional units. Power and performance are no longer closely related.
In addition to the performance improvements due to the cache, most also talked about power management. Sanjeev Jahagirdar from Intel described the efforts to reduce power consumption in the Ivy Bridge family of processors. The extensive changes resulted in significant reduction in power and also yielded better performance.
The basic architecture in the third-generation Intel core was the first to be building the 22 nm process. The intent for the design was to scale power and efficiency without sacrificing performance. They had to change the frequencies without changing the power budget. To accomplish this, they not only had to reduce the operating voltage in all other areas, but also had to run programs and profile them to get to an algorithm for power management that routed interrupts to the best available core.
This is a change from earlier interrupt controllers that just put the interrupt on the last active process. There were many trades for power and performance. They integrated more temperature sensors into the chip to get higher thermal resolution so they could address inverse temperature effects. New algorithms estimate cold spots for compensation. The sensors and firmware are evaluated and configured at test.
Idle power management required power gating the cores and the DDR drivers. The DDR states are saved in an ungated power island. They found that low voltage operation is limited by the cache performance. The older designs require a lot of voltage and the range from operating to unstable to inoperable was very small. Power can be dynamically shifted between CPU and GPU functions. In addition, they made changes in the clocking distribution and made more gated clock domains.
Jeff Rupley from AMD noted that performance has tracked the processes and power and flexibility tracked each other. Increasing the clock frequency at a given voltage requires more dynamic control of the clock network. To do this, they increased clock gating and made significant changes to the core. Power is still a driver, so the added new power gating states.
Other changes included new buffer and decoder functions, a new integer unit, a new floating point unit that can operate on 128 bit vectors, and some structural and cleanup efforts. All together, the changes amounted to a 10 percent improvement in performance, about the same as a full process generation.
They had to change to a fully synthesized design flow from their structured custom flow to handle the design size and complexity. This effort also required a redesign of many of the basic cells to be higher performance or lower power, and be more compatible with the synthesis flow. One pleasant outcome is that their design costs have dropped.
The cache algorithms changed to improve responses to cache misses. The load-store cache is coupled with the out of order execution bus unit to speed up recovery of cache misses. The new algorithms and the hardware are able to flush the cache in less time. The shared cache serves 4 cores with 2 MB of 16-way storage. The last core used now flushes its own storage space and all cache statistics to allow the cache controlled to restart more quickly.
Ranganthan Sudhaka from MIPS repeated the mantra of redesigned cache and new architectures. They added dual-port RAM to improve throughput and reduce latency to other compute units. Other functional units received updates and performance tweaks.
Because their CPU is a soft core, the core descriptions includes peripheral structures and control subsystems. Their deliverables include block diagrams, and cycle-accurate execution models as well as details of the functional units.
