Fujitsu brings new Sparc core to OOW 2012
October 2012 – In San Francisco at the Oracle Open World Conference Fujitsu had a press conference following thier keynote to announce their new Sparc processor. The next generation processor brings an architecture that is targeting large memory configuration designs. Using a traditional DDR3 interface, the device is pushing the configuration up to 512GB/core = 2TB/chip (quad core) = 8TB per server = 32TB per rack in an SMP application structure. To supplement the large memory configuration, the new design brings three additional features – (1) software applications has hardware acceleration components, (2) the design had hardware based security engines, and (3) the design uses a custom designed closed loop liquid cooling system.
The new chip is a full SOC. The device incorporates not only the CPU with a GPU acceleration, but also the full chipset control interfaces including the full north and south bridge and storage interface. This makes the device a single piece computer, as stand alone server, that has specialized hardware acceleration. These hardware modules include network transaction processing, AES and 3DES security processing (encryp and decrypt) for data going to the on-board caches, codecs, additional arithmetic acceleration and data compression. These are standard functions that support existing and new code performance optimization without code rewrites.
The cooling system is a new design on the boards. The servers utilize air cooling with a high flow rate for the memories and storage interface. The custom metal closed loop system for liquid cooling of the CPUs is designed to both aid in the channeling of airflow in the chassis and lower the operating temperature of the chips. This allows for long duty cycle operation without performance reduction in both regular chilled data centers and the new high operating temperature data centers. The configuration of the servers is a dual SOC board that has two boards mounted in a single chassis for a total of 4 processor SOCs with coolers in a standard enclosure. The design is setup as a completely self contained cooling system that will not need in application servicing so it is fully compatible with existing data center service policies.
The design is being built by Fujitsu Semiconductor and is planned for un-interrupted continuity of product after the completion of the divestiture of the business unit from Fujitsu. The design leverages the knowhow from the supercomputing design group as well as the advanced networking applications so the performance under the the Project Athena name for the next generation Sparc64 architecture. The current chip is utilizing a 10G-14G backplane interconnect and plans are to increase this to Infiniband and then up to 100G/400G in the future. The storage interface for the unit is SAS.
