Ultimate Device Technologies

December 10, 2012, International Electron Devices Meeting, San Francisco—Luc van den Hove from IMEC described the changes in device technologies that will be the core of a sustainable society. Electronics has and will continue to affect all aspects of living, and the ability to provide greater performance at ever lower costs will drive societal evolution.

Applications and drivers for technology change over time. The emergence of apps on mobile devices is driving further change. The biggest challenge for many users is how to locate and manage all of the apps. Ultra connectivity is spreading from the developed countries to the under developed, and is changing live everywhere.

Electronic wallets enable virtual stores and banks. Sensors are everywhere. For example, automobiles are now sensor platforms with detectors, radar, and other functions to enable new functions like parking assistance, and eventually autonomous driving.

The virtual is becoming reality. High bandwidth connectivity and displays are changing communications. These changes are leading to new applications and changing social life. The connections are not only between people, but now are from people to the environment, and from object to object.

Health and healthcare are of growing concern. 12 million people die of cancer a year, and healthcare costs are now 17 percent of the US gross domestic product. The issue is that many treatments are generic and post-symptom, making for the highest costs. The change to personal, predictive, and personalized medicine will require new tools and methods. Current tools and lab work can take hours or days to get results.

Instead, the medical industry should look at computers. The computers started with large, centralized mainframes, then moved to minis, PCs, and now to smart phones. Medical diagnostics have to migrate to desktop analysis, to labs on a chip, and to an add-on to a smart phone to bring the lab to the patient.

Mobile diagnostics will also move to smart, low cost health patches. These intelligent band-aids will check multiple parameters like heart rate, temperature, skin conductivity, etc., and be on flexible substrates. The patches will download their data to smart phones for analysis in the cloud. This move to early diagnosis can only happen when devices are integrated into the point of care systems.

Early disease detection requires increased sensitivity and accuracy, and better analytics. Personalized technologies will use model-based methods plus records and individualized parameters to keep you healthy. The personal “tri-corder” will interact with analytics and diagnostics and feed the data to a medical information database.

Technology is looking at an increasingly complex roadmap. There is a need to minimize power consumption for many reasons. Increased battery life, lower power density, and cooling management are just a few. The main areas for advancements are in sensors, mobile, and data centers. Consider the next generation smart phone; high-k, metal gate, 22 nm fully depleted active devices in either FinFET or FDSOI.

The challenges for the process technologies are in defining the fin, patterning the conductors and devices, stress enhancements, and step coverage for conformal doping. Beyond the 22nm node, the 14nm node will need high mobility materials. The channel will be III-V or germanium and the concentration of germanium in the silicon will change. The new materials will present many problems, chief being material brittleness and defect control.

Beyond 10 nm, the industry will have to go to a gate-all–around (GAA) topology to reduce leakage. At issue is the need to make contact to this 3-D structure. Defining the vertical fin will challenge the lithographers and new material integration will press the process people. One alternative to the existing device structures is a tunneling FET plus nano-wires. Heterojunctions will be used for carrier injection.

Even further out, we will see carbon emerge in the form of a graphene FETs using a bi-layer structure. There are a few other options to go beyond 5nm, but we will need major innovations in materials, devices, and mechanical engineering to achieve this end.

In a different direction, those who cannot afford the move to ever smaller dimensions will go to 3-D die stacks. The through silicon via is the first challenge, followed by the need for better micro-bumps. The problem is that many of the mechanical properties of the other materials like tungsten and tantalum that are used in stacking die are different from silicon.

Exploring some of the issues in stacking DRAM die on logic, shows a significant increase in performance, smaller form factor for the assembly, and the ability to integrate passives on the interposers. Changes in memory technologies will allow many technologies to be used in place of DRAM. Flash has the most challenges, but moving to a vertical structure will increase the number of cells per unit area.

Resistive RAM at 10nm can work in a 3-D stack. DRAM will need a higher-k dielectric and the FETs need redesign for lower leakage. SRAM has scaling and reliability issues at the small dimensions. Spin torque devices are candidates to replace many other technologies for memory.

The memory hierarchies will have to change to accommodate the different memory types. STT can replace SRAM and phase-change RAM, and resistive RAM might have a chance at displacing Flash. Spin logic is emerging as a potential replacement for CMOS.

When these technologies move from the lab to the cloud, everything will be more highly connected. This change in the intelligent backbone will affect wireless services, memory, storage, and other communications functions. The data center has issues with heat and bandwidth, and more data moves over optical links. As the data rates increase, more data will change from electrical to optical transport. The increase in photonics will require many new functions to be developed for multiplexers, demultiplexers, I/O conversion etc.

Materials will be a key factoring scaling, as will 3-D stacks. Lithography will have to go to EUV, which has demonstrated good resolution to 1 nm. The problems are in the sources; power and lifetime. This source has to be functional for the 14 nm node, because 193 nm double patterning is still viable for the 20 node, with double-patterning aware tools.

193nm litho is possible at the14nm node with triple patterning, but the costs will be very high, and possibly not economically feasible. The EUV tools will bring the costs of manufacturing down to acceptable levels. At the 14nm node, relaxed design rules will prevail and the lithographic-friendly rules will allow faster design implementation cycles. SRAM is a good fit for the FIN architecture. New design rules will work with regular structures and fine pitch only for metal 1.

In other areas, directed self-assembly is a distinct possibility. The lithography defines areas on the polymer bases for the features but the contact variability for self-assembled structures, as well as the distribution of the variables need to improve. This technology can get to 12nm minimum features, but will still need double patterning and a complex process to achieve results. The next nodes will define the end of lines, but these alternatives are not replacements for EUV.

The challenges in future manufacturing are partially due to the many options in the roadmap. In the past, features and topologies changed in recognizable patterns, from point contact, to planar bipolar, to CMOS. Now, there are many branches in the road that lead to sub-10 nm devices, but each path will depend on the underlying drivers. There are many applications for each technology, so the electronics community will need to connect and collaborate to get to more innovation.