ISSCC Ultra-high Speed Transceivers
February 18, 2013, ISSCC, San Francisco—The session 2 on ultra-high speed transceivers and equalizers looked at the need for lower power, higher frequency devices that can get the data rates above 20 Gb/s. A number of talks described ongoing work from companies and other organizations including Fujitsu, UC Berkeley, Broadcom, UCLA, and Rambus.
Samir Parikh from Fujitsu America described a 32 Gb/s wireline receiver with a low frequency equalizer to address the needed changes in responses in backplanes. This demonstration chip enables the increase in data rates above 25 Gb/s, enabling the advent of 100Gb systems. One of the issues is that losses in the backplane can be in the 35-40 dB range at 10 G.
High frequency equalization is adequate for many functions, but can add noise to the signal. The channel characteristics are affected by skin effects and changes in dielectric constants and average 3-4 dB per decade. The equalizers offer 20 dB per decade, so can over emphasize the high frequency components and cause overshoot and ringing.
To address this problem, a low-pass equalizer with a zero and pole close together in the low frequency area can create a good match and open the eye by reducing inter-symbol interference. A differential receiver with both CTLE and low frequency equalization can have a fairly flat response over a very wide frequency range at a low power and with reduced noise.
An integrated error sampler with offset calibration for the linear transconductor circuit uses multiple current injection paths and high-frequency peaking to equalize losses. The resulting chip in 28 nm CMOS has an area of 1200 x 275 microns and operates at 240 mW with a 0.9 V supply. The implementation has a native BER of 10 -12, so will need other error detection and correction components to address the high data volumes associated with the proposed data rates.
