Isscc 2013 Session 11Emerging Memory and Wireless

February 18, 2013, ISSCC, San Francisco—Session 11 reviewed some of the emerging and wireless technologies. Contributors were MIT, Tohoku University and NEC in Japan, Fraunhofer from Germany, CSEM and Micro Crystal from Switzerland, VTT from Finland, ST Microelectronics from Italy, Aalto University form Finland, Keio University form Japan, KAIST and Samsung from Korea, and Masdar Institute of Science and Technology UAE.

This session presented two types to technologies memories in the first half and wireless in the second. Some of the new circuits combined logic elements and non-volatile memory technologies into a single process. The overriding issue is power and energy efficiency, so the researchers included timing and enegy measurements in their work .

The ability to operate in multiple power modes and retain data in a storage circuit is invaluable in many systems. The goal for these designs is to use existing design tools and methodologies to remain within the power and timing budgets.

The researchers from Tohoku and NEC in session 11.2 considered power leakage management as one of the key design goals. The increase in leakage in the smaller process nodes causes increased power density, so they changed the design to incorporate both NVM and logic.

By including storage in the design, they reduce wire delays and the accompanying power dissipation. Their design puts the non-volatile memory on top of the logic to integrate the stack and reduce power and area as well as reduce the static power. The design required a major change in the EDA flows, since the tools didn’t have models for a magnetic thermal junction (MRAM) and didn’t have the capability to place an active device on top of the first metals.

In addition, the tools didn’t model the fine-grain power gating needed for the design. As a result, they had to develop their own NVM libraries and power gating simulation flows. A Spice model for the magnetics evolved into a special memory simulation and new leaf cells allowed the integration of the logic and memory sense amplifiers.

The designs were ported to a motion vector prediction chip for mobile applications, calling for very strict power-performance limits. The system architecture called for maximum gating of all circuits via standby processor elements. One hurdle was the clock gating, which still allowed leakage current, so they also put the power gates on standby processor elements.

The inclusion of NVM meant that the next potential candidate for an operation didn’t need standby power. They have working silicon and a new set of EDA tools that enable the integration of NVM and logic. Including cycle-by-cycle power gating resulted in a 75 percent reduction in leakage current at the cost of a slight increase in switching power and power-gating logic.

The second half of the session looked at issues like wafer-level packaging of crystals for timing generation, integrating MEMS into microwave amplifiers, contactless connectors, inductive coupling for board-board communications, wireless data and power transmission for rotating sensors, and a body-area network in fabric-based electronics.

All of these systems take advantage of very-low-power, short-range communications and require agile systems and networks for both power and communications. The new architectures for these systems allow the sensors and their data to communicate with the central base station-controller independent of the location or position of the sensors and the rest of the system.