ISSCC – Image Sensors
February 20, 2013, ISSCC, San Francisco—Image sensors are showing higher performance and embedded intelligence. The ubiquity of imagers in all areas of electronics products is producing advances in adjacent areas like medical and 3-D imaging.
A 3.4 uw CMOS sensor from Samsung and University of Michigan includes a feature-extraction algorithm for motion-triggered object-of-interest imaging. The primary issues this design addresses are temporal and spatial bandwidth limits for images. The resolution losses or complex processing increase power consumption and increase form factors. The resulting chip including motion sensing and feature extraction runs on under 55 nW with a 1.3 V pixel supply and a 0.8 V digital supply.
Another U of Michigan work uses pixel aggregation and temporal averaging for in-frame motion detection. This chip uses less than 1 uw at 5 fps, 1.1 uW at 30 fps and has a high fill factor of 38 percent. By subdividing the 128×128 imaging array into 8 x 8 sub-arrays, the imager reduces blind spots for the motion detection. A dual-mode temporal averaging scheme can detect both fast and slow motions.
Olympus is trying to address shutter lag and distortion with a 3-d stacked image sensor with in-pixel storage. Changing from a slot or rolling shutter to a global shutter allows the whole image to be captured at once, eliminating readout rolling shutter distortion. The imager needs to have a parasitic light sensitivity of at least -100 dB to eliminate light artifacts. This sensor uses a stacked 3-D architecture with the photodiodes above the storage cells, resulting in a in-pixel storage node parasitic light sensitivity of -160 dB.
The 3-D structure shields the storage nodes from light and the charges from the imager to be transferred over TSVs to the storage node and then to the readout circuits. The imager is fabricated in 0.18 micron CMOS and has a 704 x 512 pixel resolution. The sensor array has 90,112 micro bumps for interconnections . bonding is by stacking wafers.
Sony showed off a 65 nm 8 M pixel stacked imager that uses a logic substrate rather than the normal supporting, passive substrate. This change in structures allows the incorporation of high-performance logic into the sensor. The two substrates are connected through TSVs after the comparators to minimize noise, since the high-voltage transistors have lower noise. The addition of the logic to the support substrate allows the low voltage transistors to move to the logic substrate, reducing the processing steps for the combined wafers.
The separation the logic and imaging functions also allows independent process optimization and the inclusion of more logic functions in the sensor array. In addition, the total chip area is reduced by 30 percent compared to the previous generation parts in a similar process. The additional logic enables a high-dynamic range exposure system that can select or blend long and short exposures. Power is 200 mW for a 720P HDR movie.
Toyota presented a LIDAR subsystem that uses a 0.18 micron CMOS SoC to get a 100 m range with 10 cm accuracy in a time of flight sensor. The chip includes the photodiodes, conditioning circuitry, memory, and DSP for data processing. The imager includes 16 pixels for the laser detection, and 32 pixels for background-only intensity. The spatiotemporal correlation needed for accurate ranging is performed in a concurrence detection circuit that achieves a 4 ns resolution.
Panasonic developed a 2.1 M pixel imager for a single lens 3-D camera. The imager takes a single optical image and splits the individual pixel images into left and right through an integrated lenticular lens and refocuses the images through additional micro-lenses. The imager has interdigitated L-R pixels that are processed to provide side-by-side 3-D HDMI outputs. 3-D crosstalk is only 6.3 percent and brightness tracks well. The side-by side pixels on the chip eliminates the problems of pixel misalignment and changing vergence.
