Challenges and Opportunities from Collaboration
July 8, 2013, IMEC Technology Forum, San Francisco—Martin Anstice from Lam Research talked about inflection challenges and value creation opportunities from collaboration. The pace and costs of change in the semiconductor industry now make it an imperative for companies to work together.
Value in this industry comes from the semiconductors, and not from the equipment. New opportunities are coming from the move to increased connectivity in the home, automobiles, and mobile devices, and the addition of more sensors to the platforms. The capacity for storage and processing in accelerating the movement of technology and content to the consumer level.
To meet these growing demands, the industry has firmly staked out the path to scale devices to 10 nm. At the same time, we have to consider the lifecycles of processes and plan for multiple nodes and wafer sizes in the future. The new processes will need more materials engineering and an even greater diversification of processing flows. The costs for these new nodes is not meeting the demands as economics and markets diverge. The onset of the 450 mm wafers just adds the cost complexity.
Lithography will move to multiple modes, with 193, EUV, and multi-patterning all in a single flow. The underlying circuitry will have to change also. Due to cell-cell cross coupling and other parasitics, as well as cost per bit issues, NAND will become vertical. Logic will also become more 3-D and will be on complex mixtures of Si and III-V materials. DRAM architectures will change to take advantage of TSVs for power and performance issues and new capacitor dielectrics for better retention.
To meet the challenges of multiple patterning like collapse, damage, roughness, and coverage, low tension chemistries for collapse-free drying have been developed. Advanced confined plasma etch helps with better uniformity, lower defects, and the ability to handle the complex geometries. Other parts of the process flow have also changed to address the evolving process generations.
The advent of 450 mm wafers is requiring timeline synchronization with the G450 consortium, IMEC, various pilot lines and evaluation demonstrations to get to production in ’18. This synchronization is important to meet the cost expectations, increased automation, and value in the same way that the industry moved from 200 to 300 mm. The 200 to 300 mm transition was driven by IBM, but this time, the uncertainty in timing, innovation, speed, and flexibility at the different levels may make it hard to deliver the needed value.
As a result, everyone is developing 300 and 450 mm equipment in parallel. The equipment vendors are partnering with customers, consortia, and other suppliers, because the economics matter. The transition to 450 has to happen within a 2-year window, or it is a no-go for the industry. Any new standards have to be developed fairly quickly, as the current standards for 300 are all that exist. Other technical issues including planar scaling, 3-D transitions, and patterning all need further development.
Collaboration and consolidation are the keys to success. There are many opportunities and a lot of work needed to get to these next generations. Collaboration has to increase from just customers to include peers and other parts of the supply chain, research organizations, and external experts and investment groups. The equipment industry has to have a 2-3 generation lead-time to make the needed equipment in time for the industry to use it.
Successful collaboration has to be defined by trust and transparency. The combined mutual benefits will help to address the complex challenges over multiple technology and wafer size transitions. Getting the innovations and cost reductions the semiconductor industry needs will take the efforts and knowledge of many contributors.
