Scaling Beyond 10 nm
July 8, 2013, IMEC Technology Forum, San Francisco—An Steegen from Imec displayed the power, area, cost, and performance requirements for continuation of process scaling. The biggest challenge is that the increasing data traffic due to mobile and cloud drives optical scaling at the cost of power limits, increased process complexity, and cost.
As defined by Gordon Moore, each new generation needs to increase performance by 30 percent, reduce power by 20 percent, area by 50 percent, and cost by 15 percent. The industry is rushing to get to 14 and 10nm with the driver being the 0.7 area scaling. At the 10 nm node, the lithography needs to change to EUV, since the multiple patterning with immersion will require triple-pattern layout awareness and pixilated sources.
Power and performance also need to track, especially for mobile and high-end CPUs, but the possible supply reductions will be hard to achieve. The increased variability of the devices means that the supplies have to remain above 1 V to maintain performance. The alternative is to trade a lower supply voltage for much higher leakage.
One good outcome of the materials changes is that high-K dielectrics for gate oxides will enable thicker oxides and a continuation of constant capacity density. In addition, work-function engineering will allow threshold tuning. Ideally, a single gate stack will be develop for both N and P channel devices.
The 22 and 14nm nodes, work on the electrostatic behaviors lead to fully depleted devices. When we move to 10nm and below, the FIN devices will require shade control, source and drain stressors, and highly engineered gate stacks as well as work on conformal doping of the Fin. Mobility enhancement becomes atomic limited at 5 nm, so silicon channels will be replaced with Ge or III-V materials. One concern is that the high mobility materials have a narrow bandgap which increases leakage with the increased mobility.
Another issue with this small processes is a need to create structures to trap dislocations at the bottom of a groove for better defect control. The 7nm node will require some type of fully depleted structure like gate all around or SOI or strained Ge quantum well. Another limit to scaling is the date contact will always require a lot of space, even with self align structures. As a result an alternative is to move to vertical devices such as panel wires. Beyond 5nm, everything will change. Devices will require a high bandgap 2-D materials like MoS2 and WSe2.
Variability is another area that requires detailed investigations. At the sub 10nm node, slow changes like wear-out, NBTI, PBTI, and electro-migration happen at the device and wafer level and can be addressed through system design. The faster variability is related to individual devices through thermal and flicker noise, and have no easy solutions.
Channel optimizations and energy bandgap engineering are only the starting points to solve these issues. In addition, atomic level variability is exacerbated by local charge traps. The insertion of SiGe quantum well charge traps could help with reliability for NBTI. These issues will also affect the SRAMs, so some other memory structure such as STT or MRAM will be needed to manage power while maintaining performance. Other changes in the metallurgy are needed to reduce the contact resistance.
Together, all of these changes increase process complexity significantly, which also increases the costs. Getting below 10nm will require EUV on the assumption that the back end of line costs will dominate at 10nm. Scaling is slowing, so disruptive innovation is needed.
