AMD Kabini APU Details
August 26, 2013, Hot Chips Conference, Stanford, CA—Dan Bouvier from AMD described the changes and improvements in the latest AMD APU, called Kabini. This chip is a full SoC with multiple cores and integrated functions.
The latest chip is built in a 28nm process, fits into a 105 m2 die and contains 914M transistors. The chip has 4 Jaguar-class x86 cores, integrated I/O, graphics, and a memory controller. In addition, a separate microcontroller is embedded to run power management and other housekeeping tasks. See figure 1
The floorplan for the Kabini chip shows the relative placement for the various functions and the numerous interfaces built into the SoC.
The Jaguar cores are improvements on the Bobcat cores with an updated ISA and a design for process portability. Some of the enhancements are improved cache prefetch, divider, and others. The changes in the caches are a shared L2 with 16 way 2MB memory. The unified northbridge and memory controller work together to create a coherence domain. A crossbar switch connects the other subsystems, I/O, and interfaces like the PCIe and their extensions for better performance and to unload the processor.
The GPU section has some new instructions to enable more general purpose computing to the graphics engine. This new instruction set supports the Heterogeneous System Architecture (HAS) and provides two GPUs and a render engine. The graphics subsystem is capable of about 400 GFLOPS, supported by R/W cache, L1 and L2 texture planes that are coherent with each other , global atomics, and other accelerators. These function units feed 3 display engines and a video codec. See figure 2.
The Graphics Core Next (GCN) blocks in the graphics unit can perform general purpose functions as well as the graphics, and have integrated codecs and rendering.
The video outputs can support displays up to 4k as well as wireless connectivity through Miracast. The dynamic refresh rate for panels bypasses the northbridge which allows the GPU to connect directly with the DRAM controller and I/O hub.
Power management is dynamic with workload and addresses the CPUs, GPUs, and I/O. Extensive power gating is monitored and managed by an embedded microcontroller to adjust the various power states. The embedded microcontroller is tunable at the OEM-level for different thermal profiles. The controller monitors switching activity and code functions at a microsecond resolution to manage the power.
Twelve thermal sensors allow the controller to use areas of silicon in low-power states to be used as heatsinks for the operating sections. Overall, the latest chip uses half of the power of the previous versions. This power reduction is partially due to the change from 40nm to 28 nm, and to the changes in architecture. The reduced power enables operation for up to 7-8 hours on a single battery charge.
The new power profile and improved performance enable use of this chip in platforms ranging from tablets to high-end desktop machines.
