Digital Analog Design

September 23, 2013, Custom Integrated Circuits Conference, San Jose, CA—Mark Horowitz from Stanford described the steps needed to increase analog design reuse and facilitate greater design automation.

As ICs grew from simple SSI chips to today’s SoCs, the tools for digital design enabled much higher levels of abstraction, which allowed for greater automation and design reuse. These advances helped designers to meet the growing requirements for more bits, greater speeds, and lower power. The biggest problem is that the analog portions are getting harder as the underlying transistors become less precise.

One way to address the analog challenges is to go from high-precision analog circuits to lower accuracy designs that are corrected digitally. This digitally-corrected analog would address the specifications related to the full system without having to over-design the analog portions to compensate for the noise and signal degradation due to the digital components. Even with this change to digitally-corrected analog, there are still big challenges.

All design started with the basic tools of Spice and schematics in the ’70’s and all of the designs were done by tinkers. The basic flow as generate a schematic, extract netlist, and simulate in Spice. Over time, the digital flows diverged into high levels of abstraction and high level design languages and synthesis. Now, the tools generate most of a chip with Spice relegated to custom blocks and analog. The balance of the design is in standard cells and IP to make SoCs.

Even the analog portions are becoming big-D little-A designs. One problem is that the modeling is still at the transistor level for the analog portions. For the digital sections, the validation is at the digital level for all models. The analog portions are approximations within the digital realm. Integrating the analog and digital sections creates mismatches in the adaptive loops and can insert bugs like mislabeled pins, inverted polarity, missing connections, etc.

In order to make changes in the analog design flow, we need a way to encapsulate the functions and increase automation in validation, electrical rules checks (ERC), equivalence checking, and the critical parts of the assumptions and some statistical analyses. Higher level of automation will help to reduce mistakes.

One starting point is to create standard cells in analog by encapsulation of functions. the schematic needs to have a way to do an ERC to functional check, and an ERC per cell needs to call up a comprehensive set of test routines to reduce the time for validation. The design capture should include some test bench and a complete set of assumptions for the circuit.

The test bench has to include the stimuli and analytical functions for each design run at the checkout of the model. The assertions and assumptions encompass al of the use characteristics like common mode ratios, input range, operating conditions, etc. Together, this documentation can help the designer check if the cell will work within the operating limits of the new design, a fundamental function of the analog designer.

Such a validation suite for analog cells that includes test, ERC, etc. can enable a circuit book of all circuits, schematics, assertions, assumptions, and tests to allow for more design reuse. After implementing a cell catalog, the analog designers can increase their levels of abstraction to approach that of the digital designers.

Even with these design and tools changes, the analog designers need faster simulators. One way to speed up the simulations is to take advantage of the fact that analog design uses a smooth response surface and most are nearly linear or linear in a region, as opposed to the discontinuous digital simulations.

This result means that a linear system model and some deviation models could capture design intent so subtle analog design issues can be verified through simulations. Even though some circuits appear strongly non-linear, they can be linearized through some domain transformation within a coupled system.

For example, some designs convert parameters to another domain, like a PLL changes a phase to a voltage which is fed back to change the phase. A duty cycle adjuster converts duty cycle to a voltage which is processed to correct the duty cycle. These transforms can capture intent to validate the circuit model. Another example is a tunable circuit which is really comprised of two systems with pseudo outputs as intermediaries.

Such an analog abstraction to formally define equivalence captures the intent of the analog circuit. This change in abstraction levels leads to functional models that are pin accurate for simulation in Verilog-A and equivalence checkers. The models can be of low complexity but need good fidelity. Issues related these changes include signal representations which are continuous and not discrete, and non-event-driven functions like noise. These features need to be a part of the model extraction so they can be used in event-driven simulators in a piecewise linear fashion.

Implementation of an analog event simulator would have any input change become an event that is not necessarily running at constant time. The derived function matrix includes a linear regression model for equivalence checking and some gain matrix that is merged with the function matrix to represent the full system functions. The assumption of a smooth results surface means that a small number of modeling points is sufficient to accurately model the whole design. The piecewise linear sub-functions are merged through decoupled superposition. Digital controls can change the functions to make multiple equivalent circuits with changes in transfer function matrices.

If the quantized analog can be assumed to be linear, it is easy to check if it works and label the true digital inputs foe configurations. The total package of test vectors and regression lead to automated tools for inserting analog functions into SoCs.

Statistical analysis and variability aware models will allow the gain matrix to be set up to show functionality at the model level if and only if the operating parameters and assumptions are within the operating range. The designer needs to identify the parameter ranges for the functions to check and prevent known issues. A classifier can help to identify out of range valued for a process including variability and for specific applications.

Instead of having to design a new circuit, the analog designer just needs to write assertions for out of range values, a process that enables Monte Carlo analysis at the system level. The functional model checks for functional failures and helps to detect failure points.

Analog design continues to face a tools lag, because it needs high resolution for the mixed signal SoC. It is possible to make analog tools similar to digital over the next 15 years, and the higher levels of automation will minimize common mistakes through an analog verification environment, formal functional models, and correspondence. The inclusion of all nodes, and not just black-box functional descriptions of the circuit eliminates many of the hand-off losses.

Analog automation is needed because most of the new designs are just modifications of existing ones. The failures are due to the glue functions and not to the new functions because of the loss of design intent. The biggest barrier to change is current designer inertia, so the keys are to go for incremental models that model all pins and meet assertions first, then move on. Some pin models could include full functions like noise. The tools need t communicate between the analog and digital domains at sufficient accuracy levels. Building a functional model is not that hard, but building one that is high fidelity relative to Spice is hard.