Large Display Design Issues
October 5, 2013, IEEE Communications Society and Consumer Electronics Society, Santa Clara, CA—Tam Do from Pericom described the realities of large digital TV designs. The increasing screen sizes can cause problems if the digital data feeds for the screen are not carefully designed.
Data routing and transport for the larger screens is becoming an issue for timing and synchronization as the screens get to be over 50 inches. Internal video interfaces are from chi to chip while external interfaces are from device to device. The increasing display sizes can cause timing issues. A 10-bit, 120 Hz frame takes 12 lanes of transport for HD and 24 lanes for a full 1080 p HD image. Moving to 8k will require 96 lanes for data transport with LVDS (low voltage, differential signaling).
One way to handle the growing routing complexity is to change from a parallel feed to a serial one. Transport issues are relieved by using an embedded clock and 8b/10-b encoding. This solution, however, requires that the design use clock data recovery to retrieve the clock form the data stream. The change to serial data allows more flexible routing for the main data inputs and the pixel drivers.
The main external interfaces are HDMI, DVI, etc. and the inputs are usually located on a circuit board located near the edge of the panel. The power supply and other noisy circuitry are located on the other edge to minimize interference. The timing for the pixel data delivery is on a board in the middle of the display. The larger screen sized not only have greater area, but also need longer cables and a higher data rate to account for the worst case paths to the corners of the display.
The timing controls need to support the data integrity and the data volume and speeds can cause high-speed design issues for the whole system. When signals are feed into a cable, poor interfaces can cause signal degradation and delays leading to visible distortion. Bandwidth limits and reduced signal-noise ratios cause timing uncertainty and mismatches in the internal and external interfaces. The loss of signal integrity cannot be fixed after the fact.
Adding some signal conditioners like redrivers and repeaters plus additional equalization and pre-emphasis enhances the signals and overcomes insertion losses and presents an equal load to the main timing generators. The number of repeaters and redrivers will depend upon the cable lengths and the frequency of operation.
The slides from the presentation can be found on the IEEE SCV Consumer Electronics web site at : http://ewh.ieee.org/r6/scv/ce/meetings/comsec-ces/index.html
