Design and Technology Co-Optimization
September 23, 2013, CICC, San Jose, CA—Greg Yeric from ARM talked about the conjunction of design and technology in the sub-20 nm nodes and the need to use end product metrics as a part of the technology choice.
Technology scaling has been going on for a long time, and the Moore and Denard scaling tricks have been continuing their linear extrapolation of the technology trends up to ’10, or to the 45 nm node. This juggernaut of change has created silos of expertise by separating design, EDA, and the fab.
While SoC designs have taken advantage of the technology changes, they have had to deal with a growing number of design constraints to add to the power, performance, and cost issues. Even with the changes, all scaling was easy to forecast. However, at the 45 nm node, the addition of strain and other material engineering enhancements required a change in development to become lithography friendly. The reduction in pitch drove the creation of many new design rules.
These changes became more important at the 65 nm node when design for manufacturing became necessary to complete a design. The DFM push resulted in over-constraints and highly restrictive design rules. The new rules called for higher regularity, concatenation constraints, more metal 2 routing, and made blocks not able to scale.
The advent of the 32 nm node added more costs and a return to the 65 nm-type rules from the 45 nm set. Since the blocks could not scale, the designs changed to work harder at power management issues. Designs started to include power gating, and aggressive power management functions, while the foundries worked to increase the threshold voltage and make more gate length options available.
The 20 nm node requires double patterning in a litho-etch, litho-etch flow. The manufacturing steps cause greater interactions between design and fab to the point where EDA and design have to become involved in process development. Success requires much more bidirectional feedback between the various parties.
At 20 nm, designers will have the option of trading off single patterning with greater gate spacing with double patterning. Among the issues for double patterning are the odd number of lines and neighbor line optical proximity effects. The layout may need to flip cells and reduce density to get the best OPC optimizations. The router has the same issues relative to one or two tracks and the high cost of jogs in the rest of the layout.
The design and technology for the metals and fins will offer tens of thousands of options that are not part of the PDK. These technology options need evaluation for the interactions prior to the design start as the technology increases in complexity. The fins are the easy part compared to the other materials issues like III-V and high levels of strain.
The industry is still waiting for EUV to become production ready and the possibility for triple patterning is going to create a NP complex routing issue. Simple issues like self-aligned double patterning with round ends will affect the routing. EUV will make the trade offs among the technology, devices, lithography, and design metrics more significant.
One test demonstrated a 20 percent density loss due to the metal 1 keep outs. ASML and ARM are working together to more fully define the issues. The experiments include ARM layouts on an EUV tool to learn and optimize the layouts and save the desired costs and power. The hope is to be able to mix and match various lithography technologies to address the increasing number of rules and interactions. The rule evaluation calls for 60 layouts of a NAND gate to see how different structures affect final patterning and manufacturing yields.
There are other issues involved. IP may have to change to address the greater variability and technology issues. Fro example, memory will change from 6-T to 8-T plus a boosted word line to account for the variability, save power, and increase noise margins. The device variations are a function of the inverse square root of the length-width product, and SRAM is 40 percent bit cells and not logic.
The applications for the SoC designs matter, so designers need to consider the impact of their decisions on the full supply chain, or at least their own level +/- 2 levels. Designs will have to be run in a virtual fab as a virtual product to assess the cost-benefit tradeoffs. Technology issues like spacer size can reduce variability at the cost of lower density. The metal can be modified to reduce resistance to improve performance at a cost.
Manufacturers will have to their rules relative to electro-migration and possibly add metal to make the designs work. performance degradation and failure are not the same thing. When designers reduce over-design they may get lower reliability, and parameter shift due to ageing and may be outside of standard wafer parameters.
Designs will have to become adaptive to reduce the guard bands and address the variability and defects. Some part of the design will have to be built to predict and correct these changes in devices. All of these changes will increase costs and force more cost sharing across the existing design-technology silos. These practices started in the 14 nm node and will become commonplace and necessary at 10.
The greater interactions of devices and designs will encourage more random seeds for the layout and a “Monte Carlo” type of analysis of the results. The next generation routers will be much more expensive due to this added requirement. Current practices like double vias will not be allowed in cells or on metal 1, but the lack of these via structures will affect yield.
