Memory Technology Today and Tomorrow
January 29, 2014, DesignCon, Santa Clara, CA—Perry Keller from Agilent and the chair of the JEDEC JC 40.5 committee talked about the market and technology drivers facing memories. The industry can expect ongoing turmoil and change over time.
Memories are appearing in more applications, leading to consumer expectations for greater performance at lower cost. This set of drivers started with the three waves of personal compute—PC to laptop to mobile smartphone and tablets. In all cases the form factor of the main compute device got smaller and power consumption went down, from over 100W to less than 10W. At the same time, deployment increased from millions of users to billions, and the number of native applications increased in the same orders of magnitude.
The transition of personal compute to the mass population is extending even to the feature phones. All of these new applications and functions calls for changes in technical standards to address the needs of the very different markets. The drivers to reduce power have been addressed in 6 fundamental elements. Multicore processors that can run at 2 GHz handle the compute tasks, workstation-class memories like LPDDR2/3/4 provide the volatile storage, and batteries are getting better, albeit at a much lower rate than the semiconductors. High speed connectivity is now a requirement for all the devices, large, high resolution displays are in all of the various platforms, and mass storage of greater than 16 GB is everywhere.
One key is that the mass storage and main memory systems are the performance drivers. Mobile devices are approaching PCs in memory throughput and may exceed that of workstations this year. The I/O rates continue to climb. Flash can now be configured to be faster than GDDR2-5 and LPDDR faster than standard DDR4. the high-end I/O is now hitting a roll-off in rate increases.
The impact on DRAM standards is acknowledging that all memory is running into this throughput wall. Even applying graphics techniques to LPDDR to address the signaling environment cannot help for very long. Manufacturers are starting to change the interconnect by using 3-D stacks and advanced logic controllers in a single package to increase the data rates. Eventually, all memory will converge in a single interface specification.
Flash as used in UFS (universal flash storage) is moving to high-speed serial protocols and uses a low-level protocol to get from MIPI to SCSI interfaces. Memory systems will have more layered architectures to address the differing performance and power requirements of the various subsystems. Many memory systems have native 400 Gb/s interfaces.
Signaling and interconnect is segmented into 4 speed domains. For speeds up to 600 Mb/s, the low speed connections for NAND flash are simple. High-speed digital transmission lines will be used for mobile, high-speed NAND, and PCs. At speeds near 2 Gb/s, all of the technologies go to serial speed and are jitter and noise limited. For the highest speeds, hyper speed, no data eye is visible above 6Gb/s.
For example, the LPDDR4 data transfer is not reliable. A non-zero bit error rate allows for 45 – 50 ps of noise margin gain, approximately equal to the random jitter. Changes in the specifications allow for non-zero BER in this class of memory, and don’t need direct measurement. Instead testing can use a dual Dirac extrapolization. This specification change breaks the fallacy of perfect data capture. Now the spec calls for an eye mask at a BER of 10-16. the new spec calls for new implementations, new protocols, and new testing regimes to address the complex serial protocols.
Jedec has issued new compliance requirements for UFS and formal systems for compliance confirmation. As a result, the testing makers are delivering products for memory test that address the protocols, transceivers, signal integrity, and BER to evaluate the new memories. The changes in hardware and software make memory testing similar to PCIe, and new probing fixtures and other support hardware needs to be added to the testing mix.
The interconnect has also been going through changes. In ’94 the industry started to use TSOP, which changed to FBGA in ’01. In ’08, memories started to use package on package (PoP) and MCM (multi-chip modules) to increase memory density and to reduce interconnections. Last year, the first die stacks appeared. These changes are mostly following a 7-year cycle and all of the changes led to higher speeds, smaller subsystems, and increased functionality.
The changes also required new assembly infrastructure, manufacturing, and test. The increase in package and die types has caused a proliferation of probe cards and fixtures to accommodate the different package dimensions and configurations. These changes have forced design and validation strategy modifications.
